13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 6, 1999, Pages 748-760

  Medeiro, Fernando ^a   Pérez Verdú, Belén ^a   Rodríguez Vázquez, Angel ^b  

^a UNIVERSITY OF SEVILLE   (Spain)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITORS; CASCADE CONNECTIONS; CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; INTEGRATED CIRCUIT MANUFACTURE; MODEMS; SIGNAL FILTERING AND PREDICTION; SIGNAL TO NOISE RATIO; SWITCHING NETWORKS;

MULTIBIT QUANTIZATION; OVERSAMPLING RATIO; SWITCHED CAPACITOR CIRCUITS;

DELTA SIGMA MODULATION;

EID: 0344771175     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.766809     Document Type: Article

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