Process-insensitive modulated-clock voltage comparator

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3910-3913

  Taillefer, Christopher S ^a   Roberts, Gordon W ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR DESIGN; PROCESS VARIABILITY; SAMPLING RATE;

CALIBRATION; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; LOGIC DESIGN;

COMPARATOR CIRCUITS;

EID: 34547249279     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

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2. B. Razavi and B. A. Wooley, "Design Techniques for High-speed, High-Resolution Comparators," IEEE Journal of Solid-State Circuits, vol. 27. no. 12, pp.1916-1926, December 1992.
3. C. Ljuslin, J. Christiansen, A. Marchioro, O. Klingsheim, "An Integrated, 16-channel CMOS Time to Digital Converter," IEEE Transaction on Nuclear Science, vol. 41, no. 4, August 1994.
4. P. Dudek, S. Szczepanski, and J. V. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line", IEEE Transactions on Solid-State Circuits, vol. 35, no. 2, February 2000.