The 65nm Tunneling Field Effect Transistor (TFET) 0.68 μm2 6T memory cell and multi-Vth device

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 173-176

  Nirschl, Th ^a,b   Henzler, St ^a   Fischer, J ^a   Bargagli Stoffi, A ^a   Fulde, M ^a   Sterkel, M ^a   Teichmann, P ^a   Schaper, U ^b   Einfeld, J ^b   Linnenbank, C ^b   Sedlmeir, J ^b   Weber, C ^b   Heinrich, R ^b   Ostermayr, M ^b   Olbrich, A ^b   Dobler, B ^b   Ruderer, E ^b   Kakoschke, R ^b   Schrufer K ^b   Georgakos, G ^b   Hansch, W ^a   Schmitt Landsiedel, D ^a   more..

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; LOGIC DESIGN; MICROPROCESSOR CHIPS; QUANTUM THEORY; THRESHOLD VOLTAGE;

MEMORY ARRAY AREAS; QUANTUM MECHANICAL TFET; TRANSISTOR MEMORY CELL; TUNNELING FIELD EFFECT TRANSISTOR (TFET);

FIELD EFFECT TRANSISTORS;

EID: 33751413764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546613     Document Type: Conference Paper

References (12)

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