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Volumn 90, Issue 26, 2007, Pages

Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DRAIN CURRENT; ELECTRON TUNNELING; FILM THICKNESS; SEMICONDUCTING SILICON; THIN FILMS;

EID: 34547366803     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.2748366     Document Type: Article
Times cited : (142)

References (10)
  • 3
    • 17644425184 scopus 로고    scopus 로고
    • Proceedings of the Devices Research Conference
    • K. K. Bhuwalka, J. Schulze, and I. Eisele, Proceedings of the Devices Research Conference, 2004, p. 215.
    • (2004) , pp. 215
    • Bhuwalka, K.K.1    Schulze, J.2    Eisele, I.3
  • 10
    • 34547379887 scopus 로고    scopus 로고
    • International Technoogy Roadmap for Semiconductor (http://www.itrs.net/).


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.