Erratum: Revision of tunneling field-effect transistor in standard CMOS technologies (IEEE Electron Device Letters (2007) 28:4)

IEEE Electron Device Letters

Volumn 28, Issue 4, 2007, Pages 315-

  Nirschl, Th ^a   Weis, M ^a   Fulde, M ^a   Schmitt Landsiedel, D ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

EID: 77956630399     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.893272     Document Type: Erratum

References (7)

1. Th. Nirschl et al., "The tunneling field effect transistor (TFET) as an addon for ultra-low-voltage analog and digital processes," in IEDM Tech. Dig., 2004, pp. 195-198.
2. -, "The tunneling field effect transistor (TFET) used in a single-event-upset (SEU) insensitive 6 transistor SRAM cell in ultra-low voltage applications," in Proc. IEEE Conf. Nanotechnol., Munich, Germany, 2004, pp. 402-404.
3. -, "Impact of mask alignment on the tunneling field effect transistor (TFET)," in Proc. ICMTS, 2005, pp. 43-46.
4. -, "Scaling down the tunneling field effect transistor (TFET) from the 130 nm to the 65 nm CMOS process flow," in Proc. Workshop ULIS, 2005.
5. 2 6T memory cell and multi-Vth device," in Proc. 35th ESSDERC, 2005, pp. 173-176.
6. -, "Scaling properties of the tunneling field effect transistor (TFET): Device and circuit," Solid State Electron., vol. 50, no. 1, pp. 44-51, Jan. 2006.
7. P.-F. Wang et al., "Complementary tunneling transistor for low power application," Solid State Electron., vol. 48, no. 12, pp. 2281-2286, Dec. 2004.