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Volumn 46, Issue 7, 1999, Pages 1537-1544

The impact of high-κ gate dielectrics and metal gate electrodes on sub-100 nm MOSFET's

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; GATES (TRANSISTOR); PERMITTIVITY;

EID: 0032655915     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.772508     Document Type: Article
Times cited : (275)

References (21)
  • 1
    • 0031146748 scopus 로고    scopus 로고
    • Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's
    • May
    • S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's," IEEE Electron Devices Lett., vol. 18, p. 206, May 1997.
    • (1997) IEEE Electron Devices Lett. , vol.18 , pp. 206
    • Lo, S.-H.1    Buchanan, D.A.2    Taur, Y.3    Wang, W.4
  • 5
    • 0030285572 scopus 로고    scopus 로고
    • High-K dielectric materials for DRAM capacitors
    • Nov.
    • D. E. Kotecki, "High-K dielectric materials for DRAM capacitors," Semicond. Int., p. 109, Nov. 1996.
    • (1996) Semicond. Int. , pp. 109
    • Kotecki, D.E.1
  • 7
    • 0346109453 scopus 로고    scopus 로고
    • Design considerations of high-K gate dielectrics and metal gate electrodes for sub-0.1mm MOSFET's
    • B. Cheng, M. Cao, P. V. Voorde, W. Greene, H. Stork, Z. Yu, and J. C. S. Woo, "Design considerations of high-K gate dielectrics and metal gate electrodes for sub-0.1mm MOSFET's," in Proc. ESSDERC'98, 1998, p. 308.
    • (1998) Proc. ESSDERC'98 , pp. 308
    • Cheng, B.1    Cao, M.2    Voorde, P.V.3    Greene, W.4    Stork, H.5    Yu, Z.6    Woo, J.C.S.7
  • 12
    • 0030387118 scopus 로고    scopus 로고
    • Gate oxide scaling limits and projection
    • C. Hu, "Gate oxide scaling limits and projection," in IEDM Tech. Dig., 1996, p. 319.
    • (1996) IEDM Tech. Dig. , pp. 319
    • Hu, C.1
  • 13
    • 85027182855 scopus 로고
    • Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS
    • J.-M. Hwang and G. Pollack, "Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS," in IEDM Tech. Dig., 1992, p. 345.
    • (1992) IEDM Tech. Dig. , pp. 345
    • Hwang, J.-M.1    Pollack, G.2
  • 14
    • 0031236185 scopus 로고    scopus 로고
    • Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing
    • Sept.
    • H. T. Ushiki, M.-C. Yu, Y. Hirano, H. Shimada, M. Morita, and T. Ohmi, "Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing," IEEE Trans. Electron Devices, vol. 44, p. 1467, Sept. 1997.
    • (1997) IEEE Trans. Electron Devices , vol.44 , pp. 1467
    • Ushiki, H.T.1    Yu, M.-C.2    Hirano, Y.3    Shimada, H.4    Morita, M.5    Ohmi, T.6
  • 16
    • 0030416118 scopus 로고    scopus 로고
    • Accurate doping profile determination using TED/QM models extensible to sub-quarter micron nMOSFET's
    • P. V. Voorde, P. B. Griffin, Z. Yu, S.-Y. Oh, and R. W. Dutton, "Accurate doping profile determination using TED/QM models extensible to sub-quarter micron nMOSFET's," in IEDM Tech. Dig., 1996, p. 811.
    • (1996) IEDM Tech. Dig. , pp. 811
    • Voorde, P.V.1    Griffin, P.B.2    Yu, Z.3    Oh, S.-Y.4    Dutton, R.W.5
  • 17
    • 0028396643 scopus 로고
    • A simple model for quantization effects in heavily-doped silicon MOSFET's at inversion conditions
    • M. J. van Dort, P. H. Woerlee, and A. J. Walker, "A simple model for quantization effects in heavily-doped silicon MOSFET's at inversion conditions," Solid-State Electron., vol. 3, p. 411, 1994.
    • (1994) Solid-state Electron. , vol.3 , pp. 411
    • Van Dort, M.J.1    Woerlee, P.H.2    Walker, A.J.3
  • 19
    • 0041565726 scopus 로고    scopus 로고
    • Gate stack architecture analysis and channel engineering in deep sub-micron MOSFET's
    • to be published
    • A. Inani, V. R. Rao, B. Cheng, and J. C. S. Woo, "Gate stack architecture analysis and channel engineering in deep sub-micron MOSFET's," Jpn. J. Appl. Phys., to be published.
    • Jpn. J. Appl. Phys.
    • Inani, A.1    Rao, V.R.2    Cheng, B.3    Woo, J.C.S.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.