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Volumn 51, Issue 10, 2004, Pages 1733-1735

A comprehensive study on the FIBL of nanoscale MOSFETs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; PERMITTIVITY; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

EID: 5444234969     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.835022     Document Type: Article
Times cited : (33)

References (21)
  • 1
    • 0031140867 scopus 로고    scopus 로고
    • Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultrathin oxide nMOSFETs
    • May
    • S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultrathin oxide nMOSFETs," IEEE Electron Device Lett., vol. 18, pp. 209-211, May 1997.
    • (1997) IEEE Electron Device Lett. , vol.18 , pp. 209-211
    • Lo, S.H.1    Buchanan, D.A.2    Taur, Y.3    Wang, W.4
  • 6
    • 0038712510 scopus 로고    scopus 로고
    • Electrical properties and thermal stability of CVD HfOxNy gate dielectric with poly-Si gate electrode
    • Apr
    • C. H. Choi, T. S. Jeon, R. Clark, and D. L. Kwong, "Electrical properties and thermal stability of CVD HfOxNy gate dielectric with poly-Si gate electrode," IEEE Electron Device Lett., vol. 24, pp. 215-217, Apr. 2003.
    • (2003) IEEE Electron Device Lett. , vol.24 , pp. 215-217
    • Choi, C.H.1    Jeon, T.S.2    Clark, R.3    Kwong, D.L.4
  • 11
    • 0032072440 scopus 로고    scopus 로고
    • Fringing-induced barrier lowering (FIBL) in sub-100-nm MOSFETs with high-κ gate dielectrics
    • G. C. F. Yeap, S. Krishnan, and M. R. Lin, "Fringing-induced barrier lowering (FIBL) in sub-100-nm MOSFETs with high-κ gate dielectrics," Electron. Lett., vol. 34, no. 11, pp. 1150-1152, 1998.
    • (1998) Electron. Lett. , vol.34 , Issue.11 , pp. 1150-1152
    • Yeap, G.C.F.1    Krishnan, S.2    Lin, M.R.3
  • 12
    • 0034854235 scopus 로고    scopus 로고
    • New stack gate insulator structure reduce FIBL effect obviously
    • C. H. Lai, L. C. Hu, H. M. Lee, L. J. Do, and Y. C. King, "New stack gate insulator structure reduce FIBL effect obviously," in Proc. VLSI-TSA, 2001, pp. 216-219.
    • (2001) Proc. VLSI-TSA , pp. 216-219
    • Lai, C.H.1    Hu, L.C.2    Lee, H.M.3    Do, L.J.4    King, Y.C.5
  • 14
    • 5444224669 scopus 로고    scopus 로고
    • Influences of elevated extension structure on the performance of MISFETs with high-κ gate dielectric
    • Y. Kamata, M. Ono, and A. Nishiyama, "Influences of elevated extension structure on the performance of MISFETs with high-κ gate dielectric," in Proc. Int. Workshop Gate Insulator, 2001, pp. 206-209.
    • (2001) Proc. Int. Workshop Gate Insulator , pp. 206-209
    • Kamata, Y.1    Ono, M.2    Nishiyama, A.3
  • 15
    • 0036458457 scopus 로고    scopus 로고
    • Fringing-induced barrier lowering (FIBL) effects of 100-nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer
    • S. C. Lin and J. B. Kuo, "Fringing-induced barrier lowering (FIBL) effects of 100-nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer," in Proc. Int. SOI Conf., 2002, pp. 93-94.
    • (2002) Proc. Int. SOI Conf. , pp. 93-94
    • Lin, S.C.1    Kuo, J.B.2
  • 17
    • 0036564323 scopus 로고    scopus 로고
    • The effect of high-κ gate dielectrics on deep submicrometer CMOS device and circuit performance
    • May
    • N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, "The effect of high-κ gate dielectrics on deep submicrometer CMOS device and circuit performance," IEEE Trans. Electron Devices, vol. 49, pp. 826-831, May 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , pp. 826-831
    • Mohapatra, N.R.1    Desai, M.P.2    Narendra, S.G.3    Rao, V.R.4
  • 18
    • 84941334401 scopus 로고    scopus 로고
    • Detailed analysis of FIBL in MOS transistors with high-κ gate dielectrics
    • N. R. Mohapatra, M. P. Desai, and V. R. Rao, "Detailed analysis of FIBL in MOS transistors with high-κ gate dielectrics," in Proc. 16th Int. Conf. VLSI Design, 2003, pp. 99-104.
    • (2003) Proc. 16th Int. Conf. VLSI Design , pp. 99-104
    • Mohapatra, N.R.1    Desai, M.P.2    Rao, V.R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.