4H-SiC lateral double RESURF MOSFETs with Low on resistance

IEEE Transactions on Electron Devices

Volumn 54, Issue 5, 2007, Pages 1216-1223

  Noborio, Masato ^a   Suda, Jun ^a   Kimoto, Tsunenobu ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

Breakdown voltage; Device simulation; MOSFET; ON resistance; Reduced surface field (RESURF); Silicon carbide (SiC)

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC RESISTANCE; FABRICATION; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SILICON CARBIDE;

DEVICE SIMULATION; DRIFT RESISTANCE; REDUCED SURFACE FIELD;

MOSFET DEVICES;

EID: 34247873095     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.894249     Document Type: Article

References (28)

1. J. A. Cooper, Jr., M. R. Melloch, R. Singh, A. Agarwal, and J. W. Palmour, "Status and prospects for SiC power MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 4, pp. 658-664, Apr. 2002.
2. D. Peters, R. Schörner, P. Friedrichs, and D. Stephani, "4H-SiC power MOSFET blocking 1200 V with a gate technology compatible with industrial applications," Mater. Sci. Forum, vol. 433-436, pp. 769-772, 2003.
3. 2 4H-SiC power DMOSFETs," IEEE Electron Device Lett., vol. 25, no. 8, pp. 556-558, Aug. 2004.
4. M. Matin, A. Saha, and J. A. Cooper, "A self-aligned process for high-voltage, short-channel vertical DMOSFETs in 4H-SiC," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1721-1725, Oct. 2004.
5. S. Harada, M. Kato, M. Okamoto, T. Yatsuo, K. Fukuda, and K. Arai, "Low ON-resistance in inversion channel IEMOSFET formed on 4H-SiC C-face substrate," in Proc. Int. Symp. Power Semicond. Devices and ICs, 2006, pp. 125-128.
6. 2," in Proc. Int. Symp. Power Semicond. Devices and ICs, 2006, pp. 261-264.
7. K. Chatty, S. Banerjee, T. P. Chow, and R. J. Gutmann, "High-voltage lateral RESURF MOSFET's on 4H-SiC," IEEE Electron Device Lett., vol. 21, no. 7, pp. 356-358, Jul. 2000.
8. J. Appels and H. M. J. Vaes, "High voltage thin layer devices (RESURF Devices)," in IEDM Tech. Dig., 1979, pp. 238-241.
9. S. Banerjee, K. Chatty, T. P. Chow, and R. J. Gutmann, "Improved high-voltage lateral RESURF MOSFETs in 4H-SiC," IEEE Electron Device Lett., vol. 22, no. 5, pp. 209-211, May 2001.
10. S. Banerjee, T. P. Chow, and R. J. Gutmann, "1300-V 6H-SiC lateral MOSFETs with two RESURF zones," IEEE Electron Device Lett., vol. 23, no. 10, pp. 624-626, Oct. 2002.
11. 2 lateral two-zone RESURF MOSFETs in 4H-SiC with NO annealing," IEEE Electron Device Lett., vol. 25, no. 4, pp. 185-187, Apr. 2004.
12. T. Kimoto, H. Kosugi, J. Suda, Y. Kanzaki, and H. Matsunami, "Design and fabrication of RESURF MOSFETs on 4H-SiC (0001), (112̄0), and 6H-SiC (0001)," IEEE Electron Devices, vol. 52, no. 1, pp. 112-117, Jan. 2005.
13. M. Okamoto, S. Suzuki, M. Kato, T. Yatsuo, and K. Fukuda, "Lateral RESURF MOSFET fabricated on 4H-SiC (0001̄) C-face," IEEE Electron Device Lett., vol. 25, no. 6, pp. 405-407, Jun. 2004.
14. S. Suzuki, S. Harada, T. Yatsuo, R. Kosugi, J. Senzaki, and K. Fukuda, "4H-SiC lateral RESURF MOSFET with a buried channel structure," Mater. Sci. Forum, vol. 433-436, pp. 753-756, 2003.
15. P. Jamet, S. Dimitrijev, and P. Tanner, "Effects of nitridation in gate oxides grown on 4H-SiC," J. Appl. Phys., vol. 90, no. 10, pp. 5058-5063, Nov. 2001.
16. G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. K. Chanana, R. A. Weller, S. T. Pantelides, L. C. Feldman, O. W. Holland, M. K. Das, and J. W. Palmour, "Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in Nitric Oxide," IEEE Electron Device Lett., vol. 22, no. 4, pp. 176-178, Apr. 2001.
17. 2 interface," Mater. Sci. Forum, vol. 389-393, pp. 985-988, 2002.
18. K. Fukuda, M. Kato, K. Kojima, and J. Senzaki, "Effect of gate oxidation method on electrical properties of metal-oxide-semiconductor field-effect transistors fabricated on 4H-SiC C(0001̄) face," Appl. Phys. Lett., vol. 84, no. 12, pp. 2088-2090, Mar. 2004.
19. H. Yano, H. Hirao, T. Kimoto, H. Matsunami, K. Asano, and Y. Sugawara, "High channel mobility in inversion layers of 4H-SiC MOSFET's by utilizing (112̄0) face," IEEE Electron Device Lett., vol. 20, no. 12, pp. 611-613, Dec. 1999.
20. 2 4H-SiC (0001) RESURF MOSFET," IEEE Electron Device Lett., vol. 26, no. 9, pp. 649-651, Sep. 2005.
21. H. M. J. Vaes and J. A. Appels, "HV high-current lateral devices," in IEDM Tech. Dig., 1980, pp. 87-90.
22. T. Fujihira, "Theory of semiconductor superjunction devices," Jpn. J. Appl. Phys., vol. 36, no. 10, pp. 6254-6262, Oct. 1997.
23. Y. Negoro, K. Katsumoto, T. Kimoto, and H. Matsunami, "Electronic behaviors of high-dose phosphorus-ion implanted 4H-SiC (0001)," J. Appl. Phys., vol. 96, no. 1, pp. 224-228, Jul. 2004.
24. + ions implanted into 4H-SiC," J. Appl. Phys., vol. 92, no. 1, pp. 549-554, Jul. 2002.
25. Y. Negoro, T. Kimoto, and H. Matsunami, "Carrier compensation near tail region in aluminum- or boron-implanted 4H-SiC (0001)," J. Appl. Phys., vol. 98, no. 4, pp. 043 709-1-043 709-7, Aug. 2005.
26. 2O oxidation," Jpn. J. Appl. Phys. vol. 44, no. 3, pp. 1213-1218, 2005.
27. M. Noborio, Y. Kanzaki J. Suda, and T. Kimoto, "Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs," IEEE Electron Devices, vol. 52, no. 9, pp. 1954-1962, Sep. 2005.
28. 2 lateral superjunction transistor," in Proc. Int. Symp. Power Semicond. Devices and ICs, 2006, pp. 305-308.