Constraint-driven test scheduling for NoC-based systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 11, 2006, Pages 2465-2477

  Cota, Érika ^a,b   Liu, Chunsheng ^a,c  

^a IEEE   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^c UNIVERSITY OF NEBRASKA LINCOLN   (United States)

Author keywords

Network on chip (NoC); System on chip (SoC) testing; Test access mechanism (TAM); Test scheduling

Indexed keywords

NETWORK ON CHIP (NOC); NONPREEMPTIVE TEST; SYSTEM ON CHIP (SOC)TESTING; TEST ACCESS MECHANISM (TAM);

ALGORITHMS; COMMUNICATION SYSTEMS; COMPUTATIONAL METHODS; COMPUTER NETWORKS; CONSTRAINT THEORY; MICROPROCESSOR CHIPS;

INTEGRATED CIRCUITS;

EID: 33750584770     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.881331     Document Type: Article

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