The impact of NoC reuse on the testing of core-based systems

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 128-133

  Cota, E ^a   Kreutz, M ^a   Zeferino, C A ^a,b   Carro, L ^a   Lubaszewski, M ^a   Susin, A ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b Centro de Ciências Tecnológicas da Terra e do Mar Univali   (United States)

Author keywords

Bandwidth; Cost function; Network on a chip; System testing; System on a chip; Very large scale integration

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COST FUNCTIONS; INTEGRATED CIRCUIT TESTING; NETWORK-ON-CHIP; SYSTEM-ON-CHIP; VLSI CIRCUITS;

NETWORK CHARACTERISTICS; NETWORK ON A CHIP; ON-CHIP NETWORKS; PARALLELIZATIONS; SYSTEM ON A CHIP; SYSTEM TEST; SYSTEM TESTING; TEST TIME;

INTEGRATION TESTING;

EID: 84943555552     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197643     Document Type: Conference Paper

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