A complete strategy for testing an on-chip multiprocessor architecture

IEEE Design and Test of Computers

Volumn 19, Issue 1, 2002, Pages 18-28

  Aktouf, Chouki ^a,b  

^a GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

^b Grenoble Institute of Technology   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED PROCESSOR TESTING; ON-CHIP MULTIPROCESSOR ARCHITECTURE;

ALGORITHMS; INTEGRATED CIRCUIT TESTING; RANDOM ACCESS STORAGE; ROUTERS; VLSI CIRCUITS;

MULTIPROCESSING SYSTEMS;

EID: 0036143962     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.980050     Document Type: Article

References (7)

1. Execube - A new architecture for scalable MPPs
2. An introduction to the boundary-scan standard: ANSI/IEEE Std. 1149.1
3. An implementation approach of the IEEE 1149.1 for the routing test of a VLSI massively parallel architecture
4. Built-in self-test algorithm for row/column pattern sensitive faults in RAMs
5. Memory testing in a massively parallel machine
6. On the connection assignment problem of diagnosable systems
7. Functional testing and reconfiguration of MIMD machines