System level power modeling and simulation of high-end industrial network-on-chip

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn , Issue , 2004, Pages 318-323

  Bona, Andrea ^a   Zaccaria, Vittorio ^a   Zafalon, Roberte ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

Communication based low power design; Network on chip power analysis; System level energy optimization

Indexed keywords

COMMUNICATION BASED LOW POWER DESIGN; MOBILE TERMINALS (MT); NETWORK-ON-CHIP POWER ANALYSIS; SYSTEM-LEVEL ENERGY OPTIMIZATION;

BANDWIDTH; COMPUTER SIMULATION; DATA REDUCTION; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; ESTIMATION; INTERNET; NETWORK PROTOCOLS; OPTIMIZATION; REAL TIME SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 3042613418     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269258     Document Type: Conference Paper

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