SOC test scheduling using simulated annealing

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 325-330

  Zou, Wei ^a   Reddy, S M ^a   Pomeranz, I ^b   Huang, Yu ^c  

^a IA United States   (United States)

^b Purdue University   (United States)

^c MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

Simulated annealing; Testing; Very large scale integration

Indexed keywords

INTEGRATED CIRCUIT TESTING; INTEGRATION TESTING; SCHEDULING; TESTING; VLSI CIRCUITS;

BIN PACKING PROBLEM; CORE WRAPPER; RECTANGLE PACKING; SCAN CHAIN; SEQUENCE PAIR; SOC TEST SCHEDULING; TEST SCHEDULING; WRAPPER DESIGN;

SIMULATED ANNEALING;

EID: 84943540460     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197670     Document Type: Conference Paper

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