Thermal-aware test scheduling and hot spot temperature minimization for core-based systems

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 552-560

  Liu, Chunsheng ^a   Veeraraghavan, Kugesh ^a   Iyengar, Vikram ^b  

^a UNIVERSITY OF NEBRASKA LINCOLN   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP OVERHEATING; THERMAL AWARE TEST SCHEDULING; THERMAL CONSTRAINT;

ALGORITHMS; CONSTRAINT THEORY; HEATING; MICROPROCESSOR CHIPS;

SCHEDULING;

EID: 28444473414     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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