Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 544-551

  Tafaj, Enkelejda ^a   Rosinger, Paul ^a   Al Hashimi, Bashir M ^a   Chakrabarty, Krishnendu ^b  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b Duke University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

THERMAL CONSTRAINTS; THERMAL-SAFE TEST SCHEDULING;

ALGORITHMS; CONSTRAINT THEORY; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES;

SCHEDULING;

EID: 28444481316     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

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