메뉴 건너뛰기




Volumn 21, Issue 12, 2002, Pages 1517-1525

Formulating SoC test scheduling as a network transportation problem

Author keywords

Approximation algorithms; Embedded core based test scheduling; Parallel unrelated multiprocessor scheduling; Single source unsplittable flow; System on chip test; VLSI test

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; COMPUTER NETWORKS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

EID: 0036908644     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.804382     Document Type: Article
Times cited : (27)

References (24)
  • 1
    • 0032314038 scopus 로고    scopus 로고
    • Scan chain design for rest time reduction in core-based IC's
    • Oct.
    • J. Aerts and E.J. Marinissen, "Scan chain design for rest time reduction in core-based IC's," Proc. IEEE Int. Test Conf. (ITC), pp. 448-457, Oct. 1998.
    • (1998) Proc. IEEE Int. Test Conf. (ITC) , pp. 448-457
    • Aerts, J.1    Marinissen, E.J.2
  • 2
    • 0033683901 scopus 로고    scopus 로고
    • Design of system-on-a-chip test access architectures under place-and-route and power constraints
    • June
    • K. Chakrabarty, "Design of system-on-a-chip test access architectures under place-and-route and power constraints," Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 432-437, June 2000.
    • (2000) Proc. ACM/IEEE Design Automation Conf. (DAC) , pp. 432-437
    • Chakrabarty, K.1
  • 3
    • 0034292688 scopus 로고    scopus 로고
    • Test scheduling for core-based systems using mixed-integer linear programming
    • Oct.
    • _, "Test scheduling for core-based systems using mixed-integer linear programming," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1163-1174, Oct. 2000.
    • (2000) IEEE Trans. Computer-Aided Design , vol.19 , pp. 1163-1174
  • 4
    • 0012157888 scopus 로고    scopus 로고
    • Optimal test access architectures for system-on-a-chip
    • Jan.
    • _, "Optimal test access architectures for system-on-a-chip," ACM Trans. Design Automation Electron. Syst., vol. 6, pp. 26-49, Jan. 2001.
    • (2001) ACM Trans. Design Automation Electron. Syst. , vol.6 , pp. 26-49
  • 5
    • 0009679463 scopus 로고    scopus 로고
    • On the single source unsplittable flow problem
    • Y. Dinitz, N. Garg, and M.X. Goemans, "On the single source unsplittable flow problem," Combinatorica, vol. 19, pp. 17-42, 1999.
    • (1999) Combinatorica , vol.19 , pp. 17-42
    • Dinitz, Y.1    Garg, N.2    Goemans, M.X.3
  • 6
    • 0016943203 scopus 로고
    • Exact and approximate algorithms for scheduling nonidentical procesors
    • E. Horowitz and S. Sahni, "Exact and approximate algorithms for scheduling nonidentical procesors," J. ACM, vol. 23, pp. 317-327, 1976.
    • (1976) J. ACM , vol.23 , pp. 317-327
    • Horowitz, E.1    Sahni, S.2
  • 8
    • 0012118463 scopus 로고    scopus 로고
    • Online
    • IEEE P1500 Web Sire [Online]. Available: http://grouper.ieee.org/groups/1500/.
    • IEEE P1500 Web Sire
  • 9
    • 0035680777 scopus 로고    scopus 로고
    • Test wrapper and test access mechanism co-optimization for system-on-a-chip
    • Oct.
    • V. Iyengar, K. Chakrabarty, and E.J. Marinissen, "Test wrapper and test access mechanism co-optimization for system-on-a-chip," Proc. IEEE Int. Test Conf. (ITC), pp. 1023-1032; Oct. 2001.
    • (2001) Proc. IEEE Int. Test Conf. (ITC) , pp. 1023-1032
    • Iyengar, V.1    Chakrabarty, K.2    Marinissen, E.J.3
  • 10
    • 13244280761 scopus 로고    scopus 로고
    • On using rectangle packing for SOC wrapper/TAM co-optimization
    • May
    • _, "On using rectangle packing for SOC wrapper/TAM co-optimization," Proc. IEEE VLSI Test Symp. (VTS), pp. 253-258, May 2002.
    • (2002) Proc. IEEE VLSI Test Symp. (VTS) , pp. 253-258
  • 11
    • 0034995151 scopus 로고    scopus 로고
    • Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip
    • May
    • V. Iyengar and K. Chakrabarty, "Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip," Proc. IEEE VLSI Test Symp. (VTS), pp. 368-374, May 2001.
    • (2001) Proc. IEEE VLSI Test Symp. (VTS) , pp. 368-374
    • Iyengar, V.1    Chakrabarty, K.2
  • 14
    • 84962242740 scopus 로고    scopus 로고
    • On test scheduling for core-based SOC's
    • Jan.
    • S. Koranne, "On test scheduling for core-based SOC's," in Proc. VLSI Design/ASP-DAC 2002, Jan. 2002, pp. 505-510.
    • (2002) Proc. VLSI Design/ASP-DAC 2002 , pp. 505-510
    • Koranne, S.1
  • 19
    • 0012191505 scopus 로고    scopus 로고
    • A set of benchmarks for modular testing of SOC's
    • Oct.
    • _, "A set of benchmarks for modular testing of SOC's," in Proc. Int. Test Conf. (ITC), Oct. 2002.
    • (2002) Proc. Int. Test Conf. (ITC)
  • 20
    • 0034482516 scopus 로고    scopus 로고
    • A comparison of classical scheduling approaches in power-constrained block-test scheduling
    • Oct.
    • V. Muresan et al., "A comparison of classical scheduling approaches in power-constrained block-test scheduling," Proc. IEEE Int. Test Conf. (ITC), pp. 882-891, Oct. 2000.
    • (2000) Proc. IEEE Int. Test Conf. (ITC) , pp. 882-891
    • Muresan, V.1
  • 22
    • 0032307115 scopus 로고    scopus 로고
    • A novel test methodology for core-based system LSI's and a testing time minimization problem
    • Oct.
    • M. Sugihara, H. Date, and H. Yasuura, "A novel test methodology for core-based system LSI's and a testing time minimization problem," Proc. IEEE Int. Test Conf. (ITC), pp. 465-472, Oct. 1998.
    • (1998) Proc. IEEE Int. Test Conf. (ITC) , pp. 465-472
    • Sugihara, M.1    Date, H.2    Yasuura, H.3
  • 23
    • 0031367231 scopus 로고    scopus 로고
    • Test requirements for embedded core-based systems and IEEE P1500
    • Nov.
    • Y. Zorian, "Test requirements for embedded core-based systems and IEEE P1500," Proc. IEEE Int. Test Conf. (ITC), pp. 191-199, Nov. 1997.
    • (1997) Proc. IEEE Int. Test Conf. (ITC) , pp. 191-199
    • Zorian, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.