An integrated approach to testing embedded cores and interconnects using Test Access Mechanism (TAM) switch

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 4-5, 2002, Pages 475-485

  Basu, Subhayu ^a   Sengupta, Indranil ^b   Roy Chowdhury, Dipanwita ^b   Bhawmik, Sudipta ^c  

^a PRINCETON UNIVERSITY   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

^c AGERE SYSTEMS   (United States)

Author keywords

Interconnect testing; System on chip; TAM switch

Indexed keywords

ALGORITHMS; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; INTEGER PROGRAMMING; INTERCONNECTION NETWORKS; LINEAR PROGRAMMING; MICROPROCESSOR CHIPS; OPTIMIZATION; SWITCHING CIRCUITS;

EMBEDDED CORES; INTERCONNECT TESTING; SYSTEM ON CHIP BENCHMARKS; TEST ACCESS MECHANISM SWITCH;

INTEGRATED CIRCUIT TESTING;

EID: 0036694337     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1016549725661     Document Type: Article

References (10)

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