Reusing an on-chip network for the test of core-based systems

ACM Transactions on Design Automation of Electronic Systems

Volumn 9, Issue 4, 2004, Pages 471-499

  Cota, Érika ^a   Carro, Luigi ^a   Lubaszewski, Marcelo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Core based test; Network on chip; SoC test; TAM and wrapper design; Test reuse; Test scheduling

Indexed keywords

EID: 30744455761     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1027084.1027088     Document Type: Article

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