Indirect test architecture for SoC testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 7, 2004, Pages 1128-1142

  Nahvi, Mohsen ^a   Ivanov, André ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

Core based testing; Design for testability (DFT); Networks on chip (NoC); System on chip (SoC)

Indexed keywords

COMPUTATIONAL COMPLEXITY; DATA PROCESSING; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; MATHEMATICAL MODELS; PACKET NETWORKS; SWITCHING;

CORE-BASED TESTING; EMBEDDED CORES; INDIRECT TEST ARCHITECTURE; SYSTEM-ON-CHIP (SOC);

MICROPROCESSOR CHIPS;

EID: 3142607044     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.829796     Document Type: Article

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