CAS-BUS: A test access mechanism and a toolbox environment for core-based system chip testing

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 4-5, 2002, Pages 455-473

  Benabdenbi, Mounir ^a   Maroufi, Walid ^a   Marzouki, Meryem ^a  

^a NONE   (France)

Author keywords

I O bandwidth; P1500 wrappers; SoC test control; TAPed cores; Test access mechanism

Indexed keywords

INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; OPTIMIZATION; PATTERN RECOGNITION; TIME DOMAIN ANALYSIS;

CORE BASED SYSTEM CHIP TESTING; SYSTEM ON CHIP TESTING; TEST ACCESS MECHANISM;

DESIGN FOR TESTABILITY;

EID: 0036693853     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1016597624753     Document Type: Article

References (29)

1. Cas-bus: A scalable and reconfigurable test access mechanism for systems on a chip
2. Testing taped cores and wrapped cores with the same test access mechanism
3. Hierarchical test access architecture for embedded cores in an integrated circuit
4. Design of system on a chip test access architectures under place-and-route and power constraints
5. Optimal test access architectures for system on a chip
6. A novel approach for designing a hierarchical test access controller for embedded core designs in an SoC environment
7. Integration of structural test methods into an architecture specific core-test approach
8. TAM architectures and their implication on test application time
9. Test wrapper and test acces mechanism co-optimization for system on a chip
10. Scan vector compression/decompression using statistical coding
11. Test vector decompression via cyclical scan chains and its application to testing core-based designs
12. An integrated system on a chip test framework
13. Data compression
14. A structured and scalable mechanism for test access to embedded reusable cores
15. The role of test protocol in testing embedded core-based system ICs
16. Towards a standard for embedded core test: An example
17. Solving the I/O bandwidth problem in system on a chip testing
18. Controlling the CAS-BUS TAM with IEEE 1149.1 TAP: A Solution for systems on a chip testing
19. Synopsys design compiler family
20. Test features of a core-based co-processor array for video applications
21. A structured test reuse methodology for core-based system chips
22. An integrated PCI component for IEEE 1355
23. An IEEE 1149.1 based test acces architecture for ics with embedded cores
24. Addressable test ports an approach to testing embedded cores
25. Tapping into IEEE P1500 domains
26. Arithmetic coding for data compression
27. Testing the monster chip