Application-specific buffer space allocation for networks-on-chip router design

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 354-361

  Hu, Jingcao ^a   Marculescu, Radu ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; INTELLECTUAL PROPERTY; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; OPTIMIZATION; PACKET NETWORKS; ROUTERS; SIGNAL INTERFERENCE;

ADAPTIVE ROUTING; BUFFER ALLOCATION; NETWORKS-ON-CHIP; ROUTING PACKETS;

RESOURCE ALLOCATION;

EID: 16244389647     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

1. A. Hemani, et al. Network on a chip: an architecture for billion transistor era. In Proc. of the IEEE NorChip Conf., Nov. 2000.
2. A. Jalabert, et al. xPipesCompiler: a tool for instantiating application-specific NoCs. In Proc. DATE, Feb. 2004.
3. V. S. Adve and M. K. Vernon. Performance analysis of mesh interconnection networks with deterministic routing. IEEE Tran. on Parallel and Distributed Systems, 5:225-246, March 1994.
4. A. Agarwal. Limits on interconnection network performance. IEEE Tran. on Parallel and Distributed Systems, 2(4):398-412, Oct. 1991.
5. L. Benini and G. De Micheli. Networks on chip: A new paradigm for systems on chip design. In Proc. DATE, March 2002.
6. G.-M. Chiu. The odd-even turn model for adaptive routing. IEEE Tran. on Parallel and Distributed Systems, 11(7):729-738, July 2000.
7. W. J. Dally. Performance analysis of k-ary n-cube interconnection networks. IEEE Tran. on Computers, 39(6):775-785, June 1990.
8. W. J. Dally and C. L. Seitz. The torus routing chip. Distributed Computing, 1(3):187-196, 1986.
9. W. J. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In Proc. DAC, June 2001.
10. R. Dick. Embedded system synthesis benchmarks suites (E3S). http://helsinki.ee.princeton.edu/~dickrp/e3s/.
11. E. Bolotin, et al. QNoC: QoS architecture and design process for network on chip. Special issue on Networks on Chip, The Journal of Systems Architecture, Dec. 2003.
12. C. J. Glass and L. M. Ni. The turn model for adaptive routing. Journal of ACM, 41(5):874-902, Sept. 1994.
13. F. S. Hillier and G. J. Lieberman. Introduction to operations research, chapter 15, pp. 661-732. McGraw-Hill, sixth edition, 1995.
14. J. Hu and R. Marculescu. Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures. In Proc. DATE, March 2003.
15. J. Hu and R. Marculescu. Smart routing for networks-on-chip. Technical report, ECE Department, Carnegie Mellon University, March 2004. Available at http://www.ece.cmu.edu/~sld/pubs.
16. P. Kermani and L. Kleinrock. Virtual cut-through: a new computer communication switching technique. In Computer Networks, volume 3, pp. 267-286, Sept. 1979.
17. S. Murali and G. De Micheli. Bandwidth-constrained mapping of cores onto NoC architectures. In Proc. DATE, Feb. 2004.
18. L. M. Ni and P. K. McKinley. A survey of wormhole routing techniques in direct networks. IEEE Tran. on Computers, 26:62-76, Feb. 1993.
19. L.-S. Peh and W. J. Dally. A delay model for router micro-architectures. IEEE Micro, 21(1):26-34, Jan.-Feb. 2001.
20. S. Kumar et al. A network on chip architecture and design methodology. In Proc. Symposium on VLSI, April 2002.
21. Semiconductor Association. The International Technology Roadmap for Semicondutors(ITRS), 2001.
22. L. G. Valiant. A scheme for fast parallel communication. SIAM Jounal of Computing, 11(2):350-361, May 1982.