Cycle-accurate energy measurement and characterization of FPGAs

Analog Integrated Circuits and Signal Processing

Volumn 42, Issue 3, 2005, Pages 239-251

  Lee, Hyung Gyu ^a   Lee, Kyungsoo ^a   Choi, Yongseok ^a   Chang, Naehyuck ^a  

^a Seoul National University   (South Korea)

Author keywords

FPGA power measurement and characterization; High level power characterization; Low energy FPGA designs

Indexed keywords

CHARACTERIZATION; CONTROL EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; ENERGY UTILIZATION; LOGIC DESIGN; MICROPROCESSOR CHIPS; STRATEGIC PLANNING;

FPGA POWER MEASUREMENT AND CHARACTERIZATION; HIGH-LEVEL POWER CHARACTERIZATION; LOW-ENERGY FPGA DESIGNS; POWER CONSUMPTION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 16244405320     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10470-005-6758-5     Document Type: Conference Paper

References (21)

1. S. Wenande and R. Chidester, "Xilinx takes power analysis to new levels with XPower." Xcell Journal Online, vol. 41, pp. 26-27, 2001.
2. E.M. Sentovich, K.J. Singh, C. Moon, H. Savoj, R.K. Brayton, and A. Sangiovanni, "Sequential circuit design using synthesis and optimization." in Proceedings of the IEEE International Conference on Computer Design, 1992, pp. 328-333.
3. B. Lin and H.D. Man, "Low-power driven technology mapping under timing constraints." in IEEE International Conference on Computer Design, Oct. 1993, pp. 421-427.
4. C.-S. Chen, T. Hwang, and C.L. Liu, "Low power FPGA design - A re-engineering approach." in Proceeding of DAC 1997, June 1997, pp. 656-661.
5. V. George, H. Zhang, and I. Rabaey, "The design of a low energy FPGA." in Proceedings of International Symposium on Low Power Electronics and Design, Aug. 1999, pp. 188-193.
6. Altera Corporation, "Power consumption comparison: APEX 20K vs. Virtex devices." Altera Technical Brief, no. 57, Oct. 1999.
7. G.G. Cardarilli, A.D. Re, A. Nannarelli, and M. Re, "Power characterization of digital filters implemented on FPGA." in Proceedings of the International Symposium on Circuit and System, vol. 5, 2002, pp. 801-804.
8. J. Rius, A. Peidro, S. Manich, R. Rodriguez, and E. Boemo, "Measuring power and energy of CMOS circuit: A comparative analysis." in Proceedings of XVIII Conference on Design of Circuits and Integrated Systems, Feb. 2003, pp. 89-94.
9. T. Osmulski, J.T. Mudhring, B. Veale, J. M. West, H. Li, S. Vanichayobon, S.-H. Ko, J.K. Antonio, and S.K. Dhall, "A probabilistic power prediction tool for the Xilinx 4000-series FPGA." in Proceedings of the 5th International Workshop on Embedded/Distributed HPC Systems and Applications, May 2000, pp. 776-783.
10. E. A.Kusse, "Analysis and circuit design for low power programmable logic modules." in Master's thesis, Dept of Electrical Engineering and Computer Science, University of California at Berkeley, 1998.
11. B. Kumthekar, L.M. ii, and F. Somenzi, "Power optimization of FPGA-based designs without rewiring." in Proceedings of IEE Computers and Digital Techniques, vol. 147, 2000, pp. 167-174.
12. L. Shang and N.K. Jha, "High-level power modeling of CPLDs and FPGAs." in Proceedings of the IEEE International Conference on Computer Design, Sep. 2001, pp. 45-51.
13. L. Shang, A.S. Kaviani, and K. Bathala, "Dynamic power consumption in VirtexTM-II FPGA family." in Proceeding of the 2002 ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays, Feb. 2002, pp. 157-164.
14. Actel Corporation, "Power conscious design with proasic." Application Note, October 2000.
15. Altera Corporation, "Evaluation power for Altera devices." Altera Application Note, July 2001.
16. N. Chang, K. Kim, and H.G. Lee, "Cycle-accurate energy consumption measurement and analysis: Case study of ARM7TDMI." IEEE Transactions on VLSI Systems, vol. 10, pp. 146-154, 2002.
17. Fairchild Semiconductor, "FDS9926A, Dual N-Channel 2.5V Specified PowerTrench®MOSFET." Data Sheets, July 2003.
18. A.P. Chandrakasan, M. Potkonnjak, R. Mehra, J. Rabaey, and R.W. Brodersen, "Optimizing power using transformation." IEEE Transactions on CAD/ICAS, vol. 14, pp. 13-31, 1995.
19. M.J. Alexander, "Power optimization for FPGA look-up tables." in Proceedings of International Symposium on Physical Design, 1997, pp. 156-162.
20. K. Roy, "Power-dissipation driven FPGA place and route under timing constraints." IEEE Transaction on Circuits and Systems, vol. 46, no. 5, pp. 634-637, 1999.
21. Y. Joo, Y.S. Choi, H. Shim, H.G. Lee, K. Kim, and N. Chang, "Energy exploration and reduction of SDRAM memory systems." in Proceeding of Design Automaton Conference, June 2002, pp. 892-897.