Linear programming based techniques for synthesis of Network-on-Chip architectures

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 422-429

  Srinivasan, Krishnan ^a   Chatha, Karam S ^a   Konjevod, Goran ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK ELEMENTS; NETWORK-ON-CHIP (NOC); NODES; SYSTEM-ON-CHIP (SOC);

BANDWIDTH; BENCHMARKING; COMPUTER AIDED DESIGN; ELECTRIC POWER UTILIZATION; LINEAR PROGRAMMING; MICROPROCESSOR CHIPS; ROUTERS;

PACKET NETWORKS;

EID: 17644417172     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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