Trends in testing integrated circuits

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 688-697

  Vermeulen, Bart ^a   Hora, Camelia ^a   Kruseman, Bram ^a   Marinissen, Erik Jan ^a   Van Rijsinge, Robert ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; CUSTOMER SATISFACTION; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; PRODUCT DESIGN; QUALITY CONTROL; SEMICONDUCTOR DEVICE MANUFACTURE;

EMBEDDED MEMORIES; FAILURE MECHANISM; FAULT DETECTION; TEST QUALITY;

INTEGRATED CIRCUIT TESTING;

EID: 18144406931     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (42)

1. Semiconductor Industry Association. International Technology Roadmap for Semiconductors (ITRS). SIA, December 2003. (Available via http://public.itrs. net/).
2. P.K. Nag, A. Gattiker, S. Wei, R.D. Blanton, and W. Maly. Modeling the Economics of Testing: A DFT Perspective. IEEE Design & Test of Computers, 10(1):29-41, January 2002.
3. E.J. McCluskey. Quality and single-stuck faults. In Proceedings IEEE International Test Conference (ITC), page 597, October 1993.
4. W. Maly, A. Gattiker, T. Zanon, T. Vogels, R.D. Blanton, and T. Storey. Deformations of IC Structure in Test and Yield Learning. In Proceedings IEEE International Test Conference (ITC), pages 856-865, October 2003.
5. S. Ma, P. Franco, and E.J. McCluskey. An Experimental Chip to Evaluate Test Techniques Experiments Results. In Proceedings IEEE International Test Conference (ITC), pages 663-672, October 1995.
6. M. Grimaila, S. Lee, J. Dworak, K. Butler, B. Stewart, H. Balachandran, B. Houchins, V. Mathur, J. Park, L. Wang, and M. Mercer. REDO - Random Excitation and Deterministic Observation First Commercial Experiment. In Proceedings IEEE VLSI Test Symposium (VTS), pages 268-275, April 1999.
7. R. Aitken. A comparison of Defect Models for Fault Localisation with Iddq measurements, Very-low Voltage Testing for Weak CMOS Logic ICs. In Proceedings IEEE International Test Conference (ITC), pages 778-787, September 1992.
8. B. Kruseman, A. Majhi, G. Gronthoud, and S. Eichenberger. On Hazard-Free Patterns For Fine-Delay Fault Testing. In Proceedings IEEE International Test Conference (ITC), October 2004.
9. H.T. Vierhaus, W. Meyer, and U. Gloser. CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. In Proceedings IEEE International Test Conference (ITC), pages 83-91, October 1993.
10. H. Hao and E.J. McCluskey. Very-low Voltage Testing for Weak CMOS Logic ICs. In Proceedings IEEE International Test Conference (ITC), pages 275-284, October 1993.
11. W.R Daasch, K. Cota, J. McNames, and R. Madge. Neighbor selection for variance reduction in Iddq and other parametric data. In Proceedings IEEE International Test Conference (ITC), pages 92-99, October 2001.
12. R. Madge, B.H. Gob, V. Rajagopalan, C. Macchietto, R. Daasch, C. Schuermyer, C. Taylor, and D. Turner. Screening MinVDD Out-liers Using Feed-Forward Voltage Testing. In Proceedings IEEE International Test Conference (ITC), pages 673-682, Baltimore, MD, October 2002.
13. A. Kobayashi, S. Matsue, and H. Shiba. Flip-Flop Circuit with Fault Location Test Capability. In Proceedings IECEO Conference, page 962,1968. (In Japanese).
14. S. Funatsu, M. Kawai, and A. Yamada. Scan Design at NEC. IEEE Design & Test of Computers, 6(3):50-57, June 1989.
15. S.K. Goel and E.J. Marinissen. SOC Test Architecture Design for Efficient Utilization of Test Bandwidth. ACM Transactions on Design Automation of Electronic Systems, 8(4):399-429, October 2003.
16. S.K. Goel, K. Chiu, E.J. Marinissen, T. Nguyen, and S. Oostdijk. Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip. In Proceedings Design, Automation, and Test in Europe (DATE) Designers Forum, pages 108-113, Paris, France, February 2004.
17. Y. Zorian, E.J. Marinissen, and S. Dey. Testing Embedded-Core Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 130-143, Washington, DC, October 1998.
18. E.J. Marinissen et al. On IEEE P1500's Standard for Embedded Core Test. Journal of Electronic Testing: Theory and Applications, 18(4/5):365-383, August 2002.
19. F. DaSilva, Y. Zorian, L. Whetsel, K. Arabi, and R. Kapur. Overview of the IEEE P1500 Standard. In Proceedings IEEE International Test Conference (ITC), pages 988-997, Charlotte, NC, September 2003.
20. IEEE Computer Society. IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Std. 1149.1-2001. IEEE, New York, July 2001.
21. Y. Zorian and E.J. Marinissen. System Chip Test: How Will It Impact Your Design? In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 136-141, Los Angeles, June 2000.
22. V. Iyengar, K. Chakrabarty, and E.J. Marinissen. Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. In Proceedings IEEE Asian Test Symposium (ATS), pages 320-325, Tamuning, Guam, USA, November 2002.
23. H. Vranken et al. Enhanced Reduced Pin-Count Test for Full-Scan Design. In Proceedings IEEE International Test Conference (ITC), pages 738-747, Baltimore, MD, October 2001.
24. R. Dekker, F. Beenker, and L. Thijssen. Realistic Built-in Self-Test for Static RAMs. IEEE Design & Test of Computers, 6(1):26-34, January 1989.
25. J. Rajski, G. Mrugalski, and J. Tyszer. Comparative Study of CA-Based PRPOs and LFSRs with Phase Shifters. In Proceedings IEEE VLSI Test Symposium (VTS), pages 236-245, Dana Point, CA, USA, April 1999.
26. N. Tamarapalli and J. Rajski. Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. In Proceedings IEEE International Test Conference (ITC), pages 649-658, Washington, DC, USA, October 1996.
27. G. Kiefer, H. Vranken, E.J. Marinissen, and H.-J. Wunderlich. Application of Deterministic Logic BIST on Industrial Circuits. In Proceedings IEEE International Test Conference (ITC), pages 105-114, Atlantic City, NJ, USA, October 2000.
28. F. Poehl et al. Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. In Proceedings IEEE International Test Conference (ITC), pages 1211-1220, Charlotte, NC, September 2003.
29. H. Vranken, F. Hapke, S. Rogge, D. Chindamo, and E. Volkerink. ATPG Padding and ATE Vector Repeat Per Port for Reducing Test Data Volume. In Proceedings IEEE International Test Conference (ITC), pages 1069-1078, Charlotte, NC, USA, September 2003.
30. S. Comen. DfT-Focused Chip Testers: What Can They Really Do? In Proceedings IEEE International Test Conference (ITC), page 1120, Atlantic City, NJ, October 2000. (Panel position statement).
31. S.M. Perez and Y. Furukawa. Open Architecture Test System: The New Frontier. In IEEE Int. Electronics Manufacturing Technology Symposium, pages 211-214, July 2003.
32. IEEE Computer Society. IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data - Language Manual - IEEE Std. 1450.0-1999. IEEE, New York, September 1999.
33. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. IEEE Press, 1990.
34. R.D. Blanton, J.T. Chen, D. Desineni, K.N. Dwarakanath, W. Maly, and T.J. Vogels. Fault Tuples in Diagnosis of Deep-Submicron Circuits. In Proceedings International Symposium for Testing and Failure Analysis (ISTFA), pages 233-241, October 2002.
35. L.M. Huisman. Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 23(1):91-101, January 2004.
36. S. Venkataraman and S.B. Drummonds. POIROT: A logic fault diagnosis tool and its applications. In Proceedings IEEE International Test Conference (ITC), pages 253-262, October 2000.
37. Y. Sato, I. Yamazaki, H. Yamakada, T. Ikeda, and M. Takakura. A persistent diagnostic technique for unstable defects. In Proceedings IEEE International Test Conference (ITC), pages 242-249, October 2002.
38. C. Hora, R. Segers, S. Eichenberger, and M. Lousberg. An Effective Diagnosis Method to Support Yield Improvement. In Proceedings IEEE International Test Conference (ITC), pages 260-269, October 2002.
39. A. Kinra, H. Balachandran, R. Thomas, and J. Carulli. Logic Mapping on a Microprocessor. In Proceedings IEEE International Test Conference (ITC), pages 701-710, October 2000.
40. B. Benware. Logic Mapping on ASIC Products. In Proceedings International Symposium for Testing and Failure Analysis (ISTFA), pages 579-586, October 2002.
41. P. Shavikumar et al. Modelling the Effect of Technology Trends on Soft Error Rate of Combinational Logic. In Proceedings International Conference on Dependable Systems and Networks, pages 389-398, San Francisco, CA, June 2002.
42. A. Nieuwland and R. Kleihorst. The Positive Effect on IC Yield of Embedded Fault Tolerance for SEUs. In Proceedings IEEE International On-Line Testing Symposium (IOLTS), pages 75-79, Kos, Greece, July 2003.