Enhanced reduced pin-count test for full-scan design

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 738-747

  Vranken, Harald ^a   Waayers, Tom ^a   Fleury, Hervé ^b   Lelouvier, David ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; DESIGN FOR TESTABILITY; MULTIPLEXING; SHIFT REGISTERS;

ENHANCED REDUCED PIN-COUNT TEST (E-RPCT);

INTEGRATED CIRCUIT TESTING;

EID: 0035680756     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966695     Document Type: Article

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