메뉴 건너뛰기




Volumn , Issue , 2002, Pages 233-241

Fault tuples in diagnosis of deep-submicron circuits

Author keywords

Characterization; Diagnosis; Failure analysis; Fault model

Indexed keywords

DEFECTS; FAILURE ANALYSIS; LOGIC DESIGN; MATHEMATICAL MODELS; MICROELECTRONICS; POLYSILICON;

EID: 0036443193     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (43)

References (26)
  • 1
    • 0001812235 scopus 로고
    • Test routines based on symbolic logic statements
    • R. D. Eldred, "Test Routines Based on Symbolic Logic Statements," Journal of ACM, Vol. 6, No. 1, pp. 33-36, 1959.
    • (1959) Journal of ACM , vol.6 , Issue.1 , pp. 33-36
    • Eldred, R.D.1
  • 2
    • 0032684766 scopus 로고    scopus 로고
    • A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations
    • April
    • H. Takahashi, K. O. Boateng and Y. Takamatsu, "A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations," in Proc. of the IEEE VLSI Test Symposium, pp. 64-69, April 1999.
    • (1999) Proc. of the IEEE VLSI Test Symposium , pp. 64-69
    • Takahashi, H.1    Boateng, K.O.2    Takamatsu, Y.3
  • 3
    • 0019030402 scopus 로고
    • Multiple fault diagnosis in combinational circuits based on effect-cause analysis
    • June
    • M. Abramovici and M. A. Breuer, "Multiple Fault Diagnosis in Combinational Circuits Based on Effect-Cause Analysis," IEEE Transactions on Computers, C-29, No. 6, pp. 451-460, June 1980.
    • (1980) IEEE Transactions on Computers , vol.C-29 , Issue.6 , pp. 451-460
    • Abramovici, M.1    Breuer, M.A.2
  • 9
    • 0032320509 scopus 로고    scopus 로고
    • On applying non-classical defect models to automated diagnosis
    • Oct.
    • J. Saxena, et al., "On Applying Non-Classical Defect Models to Automated Diagnosis," in Proc. of the International Test Conference, pp. 748-757, Oct. 1998.
    • (1998) Proc. of the International Test Conference , pp. 748-757
    • Saxena, J.1
  • 11
    • 0033743138 scopus 로고    scopus 로고
    • A technique for logic fault diagnosis of interconnect open defects
    • April-May
    • S. Venkataraman and S. B. Drummonds, "A Technique for Logic Fault Diagnosis of Interconnect Open Defects," in Proc. of the IEEE VLSI Test Symposium, pp. 313-318, April-May 2000.
    • (2000) Proc. of the IEEE VLSI Test Symposium , pp. 313-318
    • Venkataraman, S.1    Drummonds, S.B.2
  • 13
    • 0032655688 scopus 로고    scopus 로고
    • Adaptive techniques for improving delay fault diagnosis
    • April
    • J. G. Dastidar and N. A. Touba, "Adaptive Techniques for Improving Delay Fault Diagnosis," in Proc. of the IEEE VLSI Test Symposium, pp. 168-172, April 1999.
    • (1999) Proc. of the IEEE VLSI Test Symposium , pp. 168-172
    • Dastidar, J.G.1    Touba, N.A.2
  • 14
    • 0026837728 scopus 로고
    • Empirical failure analysis and validation of fault models in CMOS VLSI
    • March
    • A. Pancholy, J. Rajski and L. McNaughton, "Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI," IEEE Design & Test of Computers, Vol. 9, No. 1, pp. 72-83, March 1992.
    • (1992) IEEE Design & Test of Computers , vol.9 , Issue.1 , pp. 72-83
    • Pancholy, A.1    Rajski, J.2    McNaughton, L.3
  • 16
    • 0024053829 scopus 로고
    • A method of fault analysis for test generation and fault diagnosis
    • July
    • H. Cox and J. Rajski, "A Method of Fault Analysis for Test Generation and Fault Diagnosis," IEEE Transactions on Computer-Aided Design, Vol. 7, pp. 813-833, July 1988.
    • (1988) IEEE Transactions on Computer-Aided Design , vol.7 , pp. 813-833
    • Cox, H.1    Rajski, J.2
  • 19
    • 33750582755 scopus 로고    scopus 로고
    • Methods for characterizing, generating test sequences for, and simulating integrated circuit faults using fault tuples and related systems and computer program products
    • U. S. Patent Application No. 09/866,357, filed May 25
    • R. D. Blanton, "Methods for Characterizing, Generating Test Sequences for, and Simulating Integrated Circuit Faults Using Fault Tuples and Related Systems and Computer Program Products", U. S. Patent Application No. 09/866,357, filed May 25, 2001.
    • (2001)
    • Blanton, R.D.1
  • 20
    • 0030284911 scopus 로고    scopus 로고
    • Rapid failure analysis using contamination-defect-fault simulation
    • Nov.
    • J. Khare and W. Maly, "Rapid Failure Analysis Using Contamination-Defect-Fault Simulation," IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 4, pp. 518-526, Nov. 1996.
    • (1996) IEEE Transactions on Semiconductor Manufacturing , vol.9 , Issue.4 , pp. 518-526
    • Khare, J.1    Maly, W.2
  • 21
    • 0021576193 scopus 로고
    • Systematic characterization of physical defects for fault analysis of MOS IC cells
    • Oct.
    • W. Maly, F.J. Ferguson and J.P. Shen, "Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells," in Proc. of the International Test Conference, pp. 390-399, Oct. 1984.
    • (1984) Proc. of the International Test Conference , pp. 390-399
    • Maly, W.1    Ferguson, F.J.2    Shen, J.P.3
  • 23
    • 0011880703 scopus 로고    scopus 로고
    • Texas Instrument, Dallas, TX
    • "TTL Databook," Texas Instrument, Dallas, TX.
    • TTL Databook
  • 24
    • 0003581572 scopus 로고    scopus 로고
    • On the generation of test patterns for combinational circuits
    • Technical Report No. 12_93, Dept. of Electrical Engineering, Virginia Polytechnic Institute and State University
    • H. K. Lee and D. S. Ha, "On the Generation of Test Patterns for Combinational Circuits," Technical Report No. 12_93, Dept. of Electrical Engineering, Virginia Polytechnic Institute and State University.
    • Lee, H.K.1    Ha, D.S.2
  • 25
    • 0035687352 scopus 로고    scopus 로고
    • Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
    • Oct.
    • T. Bartenstein, et al., "Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm," in Proc. of the International Test Conference, pp. 287-296, Oct. 2001.
    • (2001) Proc. of the International Test Conference , pp. 287-296
    • Bartenstein, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.