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Yield Estimation Model for VLSI Artwork Evaluation
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Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells
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0022201294
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Inductive Fault Analysis of MOS Integrated Circuits
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Shen, J.P.1
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0030284911
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Rapid Failure Analysis Using Contamination-Defect-Fault (CDF) Simulation
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J. Khare and W. Maly, "Rapid Failure Analysis Using Contamination-Defect-Fault (CDF) Simulation," IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 4, Nov. 1996. pp. 518-526.
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Khare, J.1
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0030647252
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Simulating the Impact of Poly-CD Wafer-Level and Die-Level Variation on Circuit Performance
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Stine, B.E.1
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Nigh, P.1
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0031376341
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Current Signatures: Application
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Proc. of ITC 1997
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A. E. Gattiker and W. Maly, "Toward understanding "IDDQ - only" fails," Proc. of ITC 1998, pp. 174-183.
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Gattiker, A.E.1
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Current-Signature-Based Analysis of Complex Test Fails
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Gattiker, A.1
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Failure Analysis of Timing and IDDq-only Failures from the Sematech Test Methods Experiment
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Nigh, P.1
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23
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A Yield Modelling and Test Oriented Taxonomy of Deep Submicron Technology Induced IC Structure Deformations
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Maly, W.1
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Study of Geometry of 0.13 μm Process Defects Using SRAM Fail Bit Maps
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A Multi-Stage Approach to Fault Identification Using Fault Tuples
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A Study of Intra-Chip Transistor Correlations
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A persistent diagnostic technique for unstable defects
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Computer-Aided Design for VLSI Circuit Manufacturability
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Diagnosing realistic bridging faults with single stuck-at information
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An Algorithm for Diagnosing Two-Line Bridging Faults in CMOS Combinational Circuits
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0029489291
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Yield Learning via Functional Test Data
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Kwon, Y.J.1
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Montañés, R.R.1
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0003804219
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Testing-Based Failure Analysis: A Critical Component of the SIA Roadmap Vision
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