Driving Baseline Yields on ASICs using Logic Mapping

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2002, Pages 579-586

  Benware, Brady R ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; FAILURE ANALYSIS; LIQUID CRYSTALS; SILICON WAFERS; SQUIDS;

ELECTRIC TESTING; LOGIC MAPPING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 1542300268     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. L.C. Wagner, "Failure Analysis of Integrated Circuits", Kluwer Academic Publishers (1999).
2. C.A. Gloor, "Embedded Memory Analysis for Standard Cell ASIC Yield Enhancement", International Symposium for Testing and Failure Analysis, pgs. 69-75 (2000).
3. J. Segal et. al., "In-line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results", International Symposium for Testing and Failure Analysis, pgs. 81-85 (2000).
4. M.L. Bushnell, V.D. Agrawal, "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits", Kluwer Academic Publishers (2000).
5. S. Venkataraman, S. Drummonds, "POIROT: A Logic Fault Diagnosis Tool and Its Applications", International Test Conference, pgs. 253-262 (2000).
6. J. Platt et. al., "Fault Diagnosis on the TMS320C80 (MVP) using FastScan", International Symposium for Testing and Failure Analysis, pgs. 127-132 (1997).
7. A. Kinra, H. Balachandran, R. Thomas, J. Carulli, "Logic Mapping on a Microprocessor", International Test Conference, pgs. 701-710 (2000).