Screening MinVDD outliers using feed-forward voltage testing

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 673-682

  Madge, R ^a   Goh, B H ^a   Rajagopalan, V ^a   Macchietto, C ^a   Daasch, R ^b   Schuermyer, C ^b   Taylor, C ^b   Turner, D ^b  

^a AGERE SYSTEMS   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; BINARY SEQUENCES; BOUNDARY CONDITIONS; CALCULATIONS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; STATISTICAL METHODS;

BINARY SEARCH; FEEDFORWARD VOLTAGE TESTING; FULL VECTOR SET SEARCH; REDUCED VECTOR SET; STATISTICAL POST-PROCESSING;

INTEGRATED CIRCUIT TESTING;

EID: 0036444838     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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13. Statistical Post Processing at Watersort: M. Rehani, R. Madge, K. Cota, LSI Logic, R.Daasch Portland State University; VTS 2002