On hazard-free patterns for fine-delay fault testing

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 213-222

  Kruseman, Bram ^a   Majhi, Ananta K ^a   Gronthoud, Guido ^a   Eichenberger, Stefan ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL SIGNAL PROCESSING; ELECTROMIGRATION; FAILURE ANALYSIS; FUNCTIONS; HAZARDS; INTEGRATED CIRCUIT TESTING; OSCILLATORS (ELECTRONIC); PROBABILITY; RELIABILITY;

ATPG; DELAY-FAULT TESTING; FAULT PATTERNS; RING OSCILLATORS;

INTEGRATED CIRCUITS;

EID: 18144381266     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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