Diagnosing Arbitrary Defects in Logic Designs Using Single Location at a Time (SLAT)

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 1, 2004, Pages 91-101

  Huisman, Leendert M ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

Defect; Diagnosis; Integrated circuit; Test

Indexed keywords

COMPUTER SOFTWARE; DEFECTS; ESTIMATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SIMULATORS;

LOGIC DEFECTS; LOGIC DIAGNOSIS;

LOGIC DESIGN;

EID: 0345869803     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.816206     Document Type: Article

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