-
1
-
-
0021482325
-
A compact igfet charge model
-
Bing. J. Sheu, D. L. Scharfetter, Chenming Hu, and D. O. Pederson, “A compact IGFET charge model,” IEEE Trans. Circuits and Systems, vol. CAS-31, no. 8, pp. 745-748, August 1984.
-
(1984)
IEEE Trans. Circuits and Systems
, vol.CAS-31
, Issue.8
, pp. 745-748
-
-
Sheu, B.J.1
Scharfetter, D.L.2
Chenming, H.3
Pederson, D.O.4
-
2
-
-
0023401686
-
Bsim: Berkeley short-channel igfet model for mos transistors
-
Bing. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “BSIM: Berkeley short-channel IGFET model for MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 22, no. 4, pp. 558-566, August 1987.
-
(1987)
IEEE Journal of Solid-State Circuits
, vol.22
, Issue.4
, pp. 558-566
-
-
Sheu, B.J.1
Scharfetter, D.L.2
Ko, P.-K.3
Jeng, M.-C.4
-
3
-
-
0024172244
-
A deep submicron mosfet model for analog/digital circuit simulations
-
San Francisco, December
-
M. C. Jeng, P. K. Ko, and C. Hu, “A deep submicron MOSFET model for analog/digital circuit simulations,” Tech. Dig. Of IEDM, pp. 114-117, San Francisco, December 1988.
-
(1988)
Tech. Dig. Of IEDM
, pp. 114-117
-
-
Jeng, M.C.1
Ko, P.K.2
Hu, C.3
-
4
-
-
0024055902
-
An engineering model for short-channel mos devices
-
K. Y. Toh, P. K. Ko, and R. G. Meyer, “An engineering model for short-channel MOS devices,” IEEE Journal of Solid-State Circuits, vol. 23, no. 4. pp. 950-958, August 1988.
-
(1988)
IEEE Journal of Solid-State Circuits
, vol.23
, Issue.4
, pp. 950-958
-
-
Toh, K.Y.1
Ko, P.K.2
Meyer, R.G.3
-
5
-
-
49749131836
-
A physical model for mosfet output resistance
-
San Francisco, December
-
J. H. Huang, Z. H. Liu, M. C. Jeng, P. K. Ko, and C. Hu, “A physical model for MOSFET output resistance,” Tech. Dig. Of IEDM, pp. 569-572, San Francisco, December 1992.
-
(1992)
Tech. Dig. Of IEDM
, pp. 569-572
-
-
Huang, J.H.1
Liu, Z.H.2
Jeng, M.C.3
Ko, P.K.4
Hu, C.5
-
6
-
-
19444362370
-
-
University of California, Berkeley
-
J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko, and C. Hu, “BSIM3 Manual”, University of California, Berkeley, 1993.
-
(1993)
BSIM3 Manual
-
-
Huang, J.H.1
Liu, Z.H.2
Jeng, M.C.3
Hui, K.4
Chan, M.5
Ko, P.K.6
Hu, C.7
-
7
-
-
0027187367
-
Threshold voltage model for deep-submicrometer mosfet's
-
Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep-submicrometer MOSFET's,” IEEE Trans. on Electron Devices, vol. 40, no. 1, pp. 86-95, January 1993.
-
(1993)
IEEE Trans. On Electron Devices
, vol.40
, Issue.1
, pp. 86-95
-
-
Liu, Z.-H.1
Hu, C.2
Huang, J.-H.3
Chan, T.-Y.4
Jeng, M.-C.5
Ko, P.K.6
Cheng, Y.C.7
-
8
-
-
84945713471
-
Hot-electron induced mosfet degradation - model, monitor, and improvement
-
February 1985, and IEEE Journal Solid-State Circuits, vol. SC-20, pp. 295-305
-
Chenming Hu, Simon C. Tam, Fu-Chieh Hsu, Ping-Keung Ko; Tung-Yi Chan; K. W. Terrill, “Hot-electron induced MOSFET degradation - Model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. ED-32, pp. 375-385, February 1985, and IEEE Journal Solid-State Circuits, vol. SC-20, pp. 295-305, February 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, pp. 375-385
-
-
Chenming, H.1
Tam, S.C.2
Hsu, F.-C.3
Ko, P.-K.4
Chan, T.-Y.5
Terrill, K.W.6
-
9
-
-
0023542548
-
The impact of gate-induced drain leakage current on mosfet scaling
-
Washington D. C., December
-
T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” Tech. Dig. Of IEDM, pp. 718-721, Washington D. C., December 1987.
-
(1987)
Tech. Dig. Of IEDM
, pp. 718-721
-
-
Chan, T.Y.1
Chen, J.2
Ko, P.K.3
Hu, C.4
-
10
-
-
0025398785
-
A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors
-
K. K. Hung, P. K. Ko, C. Hu, and Y.C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Trans. on Electron Devices, vol. 37, no. 3, pp. 654-665, March 1990.
-
(1990)
IEEE Trans. On Electron Devices
, vol.37
, Issue.3
, pp. 654-665
-
-
Hung, K.K.1
Ko, P.K.2
Hu, C.3
Cheng, Y.C.4
-
11
-
-
0025623695
-
Characterizing a single hot-electron-induced trap in submicron mosfet using random telegraph noise
-
Honolulu, Hawaii
-
P. Fang, K. K. Hung, P. K. Ko, and Chenming Hu, “Characterizing a single hot-electron-induced trap in submicron MOSFET using random telegraph noise,” Digest of Tech. Papers of Symp. on VLSI Technology, pp. 37-38, Honolulu, Hawaii, June 1990.
-
(1990)
Digest of Tech. Papers of Symp. On VLSI Technology
, pp. 37-38
-
-
Fang, P.1
Hung, K.K.2
Ko, P.K.3
Chenming, H.4
-
12
-
-
0025434759
-
A physics-based mosfet noise model for circuit simulators
-
K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A physics-based MOSFET noise model for circuit simulators,” IEEE Trans. Electron Devices, vol. 37, no. 4, pp. 1323-1333, May 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, Issue.4
, pp. 1323-1333
-
-
Hung, K.K.1
Ko, P.K.2
Hu, C.3
Cheng, Y.C.4
-
13
-
-
0030269375
-
Mosfet carrier mobility model based on gate oxide thickness, threshold and gate voltages
-
Kai Chen, H. C. Wann, J. Dunster, P. K. Ko, Chenming Hu, and M. Yoshida, “MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages,” Solid-State Electronics, pp. 1515-1518, October 1996.
-
(1996)
Solid-State Electronics
, pp. 1515-1518
-
-
Chen, K.1
Wann, H.C.2
Dunster, J.3
Ko, P.K.4
Chenming, H.5
Yoshida, M.6
-
14
-
-
0032138426
-
A unified mosfet channel charge model for device modeling in circuit simulation
-
Yuhua Cheng, Kai Chen, K. Imai, and Chenming Hu, “A unified MOSFET channel charge model for device modeling in circuit simulation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 641-644, August 1998.
-
(1998)
IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems
, pp. 641-644
-
-
Cheng, Y.1
Chen, K.2
Imai, K.3
Chenming, H.4
-
15
-
-
0031078092
-
A physical and scalable i-v model in bsim3v3 for analog/digital circuit simulation
-
Yuhau Cheng, Mie-Chie Jeng, Zhihong Liu, Mansun Chan, J. H. Huang, Kai Chen, P. K. Ko, and Chenming Hu, “A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation,” IEEE Trans. Electron Devices, pp. 277-287, 1997.
-
(1997)
IEEE Trans. Electron Devices
, pp. 277-287
-
-
Cheng, Y.1
Jeng, M.-C.2
Liu, Z.3
Chan, M.4
Huang, J.H.5
Chen, K.6
Ko, P.K.7
Chenming, H.8
-
17
-
-
85115984842
-
Bsim3v3.2 Mosfet model - Users manual memorandum no. Ucb/erl m98/51
-
Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K. Ko, and Chenming Hu, “BSIM3v3.2 MOSFET model - Users’ manual”, Memorandum No. UCB/ERL M98/51. Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August 21, 1998.
-
(1998)
Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August
, pp. 21
-
-
Liu, W.1
Jin, X.2
Chen, J.3
Jeng, M.-C.4
Liu, Z.5
Cheng, Y.6
Chen, K.7
Chan, M.8
Hui, K.9
Huang, J.10
Robert, T.11
Ko, P.K.12
Chenming, H.13
-
18
-
-
0003906956
-
-
Memorandum No. UCB/ERL M00/38, Electronics Research Laboratory, College of Engineering, University of California, Berkeley. August 3
-
Weidong Liu, Xiaodong Jin, Kanyu M. Cao, and Chenming Hu, “BSIM4.0.0 MOSFET model - User’s manual,” Memorandum No. UCB/ERL M00/38, Electronics Research Laboratory, College of Engineering, University of California, Berkeley. August 3, 2000.
-
(2000)
BSIM4.0.0 MOSFET Model - Users manual
-
-
Liu, W.1
Jin, X.2
Cao, K.M.3
Chenming, H.4
-
19
-
-
0032277985
-
An effective gate resistance model for cmos rf and noise modeling
-
San Francisco, December
-
Xiaodong Jin, Jia-Jiunn Ou, Chin-Hung Chen, Weidong Liu, M. Deen, P. R. Gray, and Chenming Hu, “An effective gate resistance model for CMOS RF and noise modeling,” Tech. Dig. Of IEDM, pp. 961-964, San Francisco, December 1998.
-
(1998)
Tech. Dig. Of IEDM
, pp. 961-964
-
-
Jin, X.1
Jia-Jiunn, O.2
Chen, C.-H.3
Liu, W.4
Deen, M.5
Gray, P.R.6
Chenming, H.7
-
20
-
-
0033281314
-
Submicron cmos thermal noise modeling from an rf perspective
-
Jia-Jiunn Ou, Xiaodong Jin, Chenming Hu, and P. R. Gray, “Submicron CMOS thermal noise modeling from an RF perspective,” VLSI Technology Symposium, pp.151 -152, 1999.
-
(1999)
VLSI Technology Symposium
-
-
Jia-Jiunn, O.1
Jin, X.2
Chenming, H.3
Gray, P.R.4
-
21
-
-
0032625531
-
An efficient and accurate compact model for thin-oxide mosfet intrinsic capacitance considering the finite charge layer thickness
-
Weidong Liu, Xiaodong Jin, Ya-Chin King, and C. Hu, “An efficient and accurate compact model for thin-oxide MOSFET intrinsic capacitance considering the finite charge layer thickness,” IEEE Trans. Electron Devices, pp.1070-1072, May 1999.
-
(1999)
IEEE Trans. Electron Devices
, pp. 1070-1072
-
-
Liu, W.1
Jin, X.2
King, Y.-C.3
Hu, C.4
-
22
-
-
0034453479
-
Bsim4 gate leakage model including source-drain partition
-
San Francisco, December
-
Kanyu M. Cao, W. C. Lee, Weidong Liu, Xiaodong Jin, Pin Su, S. K. H. Fung, Judy X. An, B. Yu, and Chenming Hu, “BSIM4 gate leakage model including source-drain partition,” Tech. Dig. Of IEDM, pp. 815-818, San Francisco, December 2000.
-
(2000)
Tech. Dig. Of IEDM
, pp. 815-818
-
-
Cao, K.M.1
Lee, W.C.2
Liu, W.3
Jin, X.4
Pin, S.5
Fung, S.K.H.6
An, J.X.7
Yu, B.8
Chenming, H.9
-
23
-
-
0033325337
-
Modeling of pocket implanted mosfets for anomalous analog behavior
-
Washington D. C., December
-
Kanyu Mark Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth, Keith Green, John Krick, Tom Vrotsos, and Chenming Hu, “Modeling of pocket implanted MOSFETs for anomalous analog behavior,” Tech. Dig. Of IEDM, pp. 171-174, Washington D. C., December 1999.
-
(1999)
Tech. Dig. Of IEDM
, pp. 171-174
-
-
Cao, K.M.1
Liu, W.2
Jin, X.3
Vasanth, K.4
Green, K.5
Krick, J.6
Vrotsos, T.7
Chenming, H.8
-
24
-
-
1442336332
-
Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded soi mosfets
-
Mansun Chan, Pin Su, Hui Wan, C. H. Lin, Samuel K.-H. Fung, A. M. Niknejad, Chenming Hu, and P. K. Ko, “Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs, ” Solid State Electronics, pp. 969-978, June 2004.
-
(2004)
Solid State Electronics
, pp. 969-978
-
-
Chan, M.1
Pin, S.2
Wan, H.3
Lin, C.H.4
Fung, S.K.-H.5
Niknejad, A.M.6
Chenming, H.7
Ko, P.K.8
-
25
-
-
0035310019
-
Soi thermal impedance extraction methodology and its significance for circuit simulation
-
Wei Jin, Weidong Liu, S. K. H. Fung, P. C. Chan, and Chenming Hu, “SOI thermal impedance extraction methodology and its significance for circuit simulation,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 730-736, April 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.4
, pp. 730-736
-
-
Jin, W.1
Liu, W.2
Fung, S.K.H.3
Chan, P.C.4
Chenming, H.5
-
26
-
-
44149095382
-
Rf modeling for fdsoi mosfet and self heating effect on rf parameter extraction
-
Hui Wan, Pin Su, Samuel K. H. Fung, A. Niknejad, and Chenming Hu, “RF modeling for FDSOI MOSFET and self heating effect on RF parameter extraction,” NanoTech Workshop on Compact Modeling, 2002.
-
(2002)
Nanotech Workshop on Compact Modeling
-
-
Wan, H.1
Pin, S.2
Fung, S.K.H.3
Niknejad, A.4
Chenming, H.5
-
27
-
-
85115973944
-
K. V. Subramanian, tsu-jae king, j. Bokor, and chenming hu, ”sub-50 nm finfet: Pmos”, tech. Dig. Of iedm
-
Washington D. C., December
-
Xuejue Huang, Wen-Chin Lee, Charles Kuo, D. Hisamoto, Leland Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Yang-Kyu Choi, K. Asano, K, V. Subramanian, Tsu-Jae King, J. Bokor, and Chenming Hu, ”Sub-50 nm FinFET: PMOS ”, Tech. Dig. Of IEDM, pp. 67-70, Washington D. C., December 1999.
-
(1999)
Pp
, vol.67-70
-
-
Huang, X.1
Lee, W.-C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
Anderson, E.7
Takeuchi, H.8
Choi, Y.-K.9
Asano, K.10
-
28
-
-
38649083893
-
Bsim-mg: A versatile multi-gate fet model for mixed-signal design,”
-
Kyoto, June
-
M. V. Dunga, Chung-Hsun Lin, D. D. Lu, Weize Xiong, C. R. Cleavelin, P. Patruno, Jiunn-Ren Hwang, Fu-Liang, A. M. Niknejad, and Chenming Hu “BSIM-MG: A versatile multi-gate FET model for mixed-signal design,” VLSI Technology Symposium, pp. 60-61, Kyoto, June 2007.
-
(2007)
VLSI Technology Symposium
, pp. 60-61
-
-
Dunga, M.V.1
Chung-Hsun Lin, D.D.L.2
Xiong, W.3
Cleavelin, C.R.4
Patruno, P.5
Hwang, J.-R.6
Fu-Liang, A.M.N.7
Chenming, H.8
-
29
-
-
0003906956
-
Bsim4.0.0 mosfet model - user’s manual
-
Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August S
-
Weidong Liu, Xiaodong Jin, Kanyu M. Cao, and Chenming Hu, “BSIM4.0.0 MOSFET Model - User’s Manual,” Memorandum No. UCB/ERL MGG/3S, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August S, 2000.
-
(2000)
Memorandum No. UCB/ERL MGG/3S
-
-
Liu, W.1
Jin, X.2
Cao, K.M.3
Chenming, H.4
-
30
-
-
85115982758
-
-
University of California, Berkeley
-
Tanvir Hasan Morshed, Wenwei Morgan Yang, Mohan V. Dunga, Xuemei Jane Xi, Jin He, Weidong Liu, Kanyu M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun Chan, Ali M. Niknejad, and Chenming Hu, “BSIM4.6.4 User’s Manual,” University of California, Berkeley, http://www-device.eecs.berkeley.edu/~bsimS/bsim4.html, August 2009.
-
(2009)
BSIM4.6.4 User’s Manual
-
-
Morshed, T.H.1
Yang, W.M.2
Dunga, M.V.3
Xi, X.J.4
He, J.5
Liu, W.6
Cao, K.M.7
Jin, X.8
Jeff, J.O.9
Chan, M.10
Niknejad, A.M.11
Chenming, H.12
-
31
-
-
0027187367
-
Threshold voltage model for deep-submicrometer mosfet's
-
January
-
Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep-submicrometer MOSFET's,” IEEE Trans. on Electron Devices, vol. 40, no. 1, pp. 86-95, January 1995.
-
(1995)
IEEE Trans. On Electron Devices
, vol.40
, Issue.1
, pp. 86-95
-
-
Liu, Z.-H.1
Hu, C.2
Huang, J.-H.3
Chan, T.-Y.4
Jeng, M.-C.5
Ko, P.K.6
Cheng, Y.C.7
-
32
-
-
85115942921
-
-
edited by Michael S. Shur and Tor A. Fjeldly, ISBN: 981-02-4280-8, World Scientific
-
Weidong Liu and Chenming Hu, “BSIMSvS MOSFET Model” - Silicon and Beyond: Advanced Device Models and Circuit Simulators,” edited by Michael S. Shur and Tor A. Fjeldly, pp. 1-51, ISBN: 981-02-4280-8, World Scientific, 2000.
-
(2000)
Bsimsvs MOSFET Model - Silicon and Beyond: Advanced Device Models and Circuit Simulators
, pp. 1-51
-
-
Liu, W.1
Chenming, H.2
-
33
-
-
85115927802
-
Bsimsvs.2 mosfet model - users manual memorandum no. Ucb/erl m98/51
-
University of California, Berkeley, August 21
-
Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K. Ko, and Chenming Hu, “BSIMSvS.2 MOSFET model - Users’ manual,” Memorandum No. UCB/ERL M98/51. Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August 21, 1998.
-
(1998)
Electronics Research Laboratory, College of Engineering
-
-
Liu, W.1
Jin, X.2
Chen, J.3
Jeng, M.-C.4
Liu, Z.5
Cheng, Y.6
Chen, K.7
Chan, M.8
Hui, K.9
Huang, J.10
Robert, T.11
Ko, P.K.12
Chenming, H.13
-
34
-
-
0033325337
-
Modeling of pocket implanted mosfets for anomalous analog behavior
-
Kanyu Mark Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth, Keith Green, John Krick, Tom Vrotsos, and Chenming Hu, “Modeling of pocket implanted MOSFETs for anomalous analog behavior”, Tech. Dig. Of IEDM, pp. 171-174, 1999.
-
(1999)
Tech. Dig. Of IEDM
, pp. 171-174
-
-
Cao, K.M.1
Liu, W.2
Jin, X.3
Vasanth, K.4
Green, K.5
Krick, J.6
Vrotsos, T.7
Chenming, H.8
-
35
-
-
0018683243
-
Characterization of the electron mobility in the inverted <100> si surface
-
Anant G. Sabnis, and James T. Clemens, “Characterization of the electron mobility in the inverted <100> Si surface,” Tech. Dig. Of IEDM, pp. 18-21, 1979.
-
(1979)
Tech. Dig. Of IEDM
, pp. 18-21
-
-
Sabnis, A.G.1
Clemens, J.T.2
-
36
-
-
0022688857
-
Inversion-layer capacitance and mobility of very think gate-oxide mosfets,”
-
ED-SS, no. S
-
Mong-Song Liang, Jeong Yeol Choi, Ping-Keung Ko, and Chenming Hu, “Inversion-layer capacitance and mobility of very think gate-oxide MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-SS, no. S, pp. 409-41S, March 1986.
-
(1986)
IEEE Trans. Electron Devices
, pp. 409-415
-
-
Liang, M.-S.1
Choi, J.Y.2
Ko, P.-K.3
Chenming, H.4
-
37
-
-
49949134400
-
Effects of diffusion current on characteristics of metal-oxide (Insulator)-semiconductor transistors
-
H. C. Pao, and C. T. Sah, “Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors,” Solid-State Electronics, vol. 9, pp. 927-937, 1966.
-
(1966)
Solid-State Electronics
, vol.9
, pp. 927-937
-
-
Pao, H.C.1
Sah, C.T.2
-
38
-
-
0017932965
-
A charge sheet model of the mosfet
-
J. R. Brews, “A charge sheet model of the MOSFET,” Solid-State Electronics, vol. 21, pp. 345-355, 1978.
-
(1978)
Solid-State Electronics
, vol.21
, pp. 345-355
-
-
Brews, J.R.1
-
39
-
-
85115942921
-
Bsim3v3 mosfet model
-
edited by Michael S. Shur and Tor A. Fjeldly, pp., ISBN: 981-02-4280-8, World Scientific
-
Weidong Liu, and Chenming Hu, “BSIM3v3 MOSFET Model” - Silicon and Beyond: Advanced Device Models and Circuit Simulators, edited by Michael S. Shur and Tor A. Fjeldly, pp. 1-31, ISBN: 981-02-4280-8, World Scientific, 2000.
-
(2000)
- Silicon and Beyond: Advanced Device Models and Circuit Simulators
, pp. 1-31
-
-
Liu, W.1
Chenming, H.2
-
41
-
-
0344007420
-
-
University of California, Berkeley, March
-
J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko, and C. Hu, “BSIM3 Version 2.0 User’s Manual,” University of California, Berkeley, March 1994.
-
(1994)
BSIM3 Version 2.0 Users Manual
-
-
Huang, J.H.1
Liu, Z.H.2
Jeng, M.C.3
Hui, K.4
Chan, M.5
Ko, P.K.6
Hu, C.7
-
42
-
-
49749131836
-
A physical model mosfet output resistance
-
San Francisco, December
-
J. H. Huang, Z. H. Liu, M. C. Jeng, P. Ko, and C. Hu, “A physical model MOSFET output resistance,” Tech. Dig. Of IEDM, pp. 569-572, San Francisco, December 1992.
-
(1992)
Tech. Dig. Of IEDM
, pp. 569-572
-
-
Huang, J.H.1
Liu, Z.H.2
Jeng, M.C.3
Ko, P.4
Hu, C.5
-
43
-
-
0031078092
-
A physical and scalable i-v model in bsim3v3 for analog/digital circuit simulation
-
Y. Cheng, M. Jeng, Z. Liu, J. H. Hang, M. Chan, K. Chen, P. Ko, and C. Hu, “A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation,” IEEE Tran. Electron Devices, vol. 44, pp. 277-287, 1997.
-
(1997)
IEEE Tran. Electron Devices
, vol.44
, pp. 277-287
-
-
Cheng, Y.1
Jeng, M.2
Liu, Z.3
Hang, J.H.4
Chan, M.5
Chen, K.6
Ko, P.7
Hu, C.8
-
44
-
-
0003906956
-
Bsim3v3.2 mosfet model - users manual,”
-
College of Engineering, the University of California at Berkeley
-
Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K. Lo, and Chenming Hu, “BSIM3v3.2 MOSFET MODEL - Users’ Manual,” Memorandum No. UCB/ERL M98/51. Electronics Research Laboratory, College of Engineering, the University of California at Berkeley, August 1998.
-
(1998)
Memorandum No. UCB/ERL M98/51. Electronics Research Laboratory
-
-
Liu, W.1
Jin, X.2
Chen, J.3
Jeng, M.-C.4
Liu, Z.5
Cheng, Y.6
Chen, K.7
Chan, M.8
Hui, K.9
Huang, J.10
Robert, T.11
Lo, P.K.12
Chenming, H.13
-
45
-
-
0033325337
-
Modeling of pocket implanted mosfets for anomalous analog behavior
-
Washington D. C., December
-
Kanyu Mark Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth, Keith Green, John Krick, Tom Vrotsos, and Chenming Hu, “Modeling of pocket implanted MOSFETs for anomalous analog behavior,” Tech. Dig. Of IEDM, pp. 171-174, Washington D. C., December 1999.
-
(1999)
Tech. Dig. Of IEDM
, pp. 171-174
-
-
Cao, K.M.1
Liu, W.2
Jin, X.3
Vasanth, K.4
Green, K.5
Krick, J.6
Vrotsos, T.7
Chenming, H.8
-
46
-
-
84945713471
-
Hot-electron induced mosfet degradation - model, monitor, improvement
-
C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan, and K.W. Kyle, “Hot-Electron Induced MOSFET Degradation - Model, Monitor, Improvement,” IEEE Trans. Electron Devices, vol. 32, pp. 375-385, 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.32
, pp. 375-385
-
-
Hu, C.1
Tam, S.2
Hsu, F.C.3
Ko, P.K.4
Chan, T.Y.5
Kyle, K.W.6
-
47
-
-
85115977538
-
Fundamentals of solid-state electronics (Fsse)
-
Chih-Tang Sah, “Fundamentals of Solid-State Electronics (FSSE),” World Scientific Publishing Co., pp. 474-497, 1991.
-
(1991)
World Scientific Publishing Co
, pp. 474-497
-
-
Sah, C.-T.1
-
48
-
-
85115982758
-
-
The University of California atBerkeley
-
Tanvir H. Morshed, Wenwei Morgan Yang, Mohan V. Dunga, Xuemei Jane Xi, Jin He, Weidong Liu, Kanyu M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun Chan, Ali M. Niknejad, and Chenming Hu, “BSIM4.6.4 User’s Manual,” The University of California atBerkeley, http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html. 2009.
-
(2009)
BSIM4.6.4 User’s Manual
-
-
Morshed, T.H.1
Yang, W.M.2
Dunga, M.V.3
Xi, X.J.4
He, J.5
Liu, W.6
Cao, K.M.7
Jin, X.8
Jeff, J.O.9
Chan, M.10
Niknejad, A.M.11
Chenming, H.12
-
50
-
-
0032666009
-
Evidence of hole direct tunneling through ultrathin gate oxide using p poly-sige gate
-
Wen-Chin Lee, Tsu-Jae King, and Chenming Hu, “Evidence of hole direct tunneling through ultrathin gate oxide using P poly-SiGe gate,” IEEE EDL, vol. 20, no. 6, pp. 268-271, June, 1999.
-
(1999)
IEEE EDL
, vol.20
, Issue.6
, pp. 268-271
-
-
Lee, W.-C.1
King, T.-J.2
Chenming, H.3
-
51
-
-
84948456795
-
Studying the impact of gate tunneling on dynamic behaviors of partially-depleted soi cmos using bsimpd
-
Pin Su, Samuel K. H. Fung, Weidong Liu, and Chenming Hu, “Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD,” Proceedings of the International Symposium on Quality Electronic Design (ISQED), pp. 487-491, 2002.
-
(2002)
Proceedings of the International Symposium on Quality Electronic Design
, pp. 487-491
-
-
Pin, S.1
Fung, S.K.H.2
Liu, W.3
Chenming, H.4
-
52
-
-
79956033267
-
Direct tunneling leakage current and scalability of alternative gate dielectrics
-
Yee-Chia Yeo, Tsu-Jae King, and Chenming Hu, “Direct tunneling leakage current and scalability of alternative gate dielectrics,” Applied Physics Letters, 81(11), pp. 2091-2093, 2002.
-
(2002)
Applied Physics Letters
, vol.81
, Issue.11
, pp. 2091-2093
-
-
Yeo, Y.-C.1
King, T.-J.2
Chenming, H.3
-
53
-
-
0034453479
-
Bsim4 gate leakage model including source-drain partition
-
San Francisco, December
-
K. M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, “BSIM4 gate leakage model including source-drain partition,” Tech. Dig. Of IEDM, pp. 815 - 818, San Francisco, December 2000.
-
(2000)
Tech. Dig. Of IEDM
-
-
Cao, K.M.1
Lee, W.-C.2
Liu, W.3
Jin, X.4
Su, P.5
Fung, S.K.H.6
An, J.X.7
Yu, B.8
Hu, C.9
-
54
-
-
84937647715
-
A new semiconductor tetrode, the surface-potential controlled transistor
-
Chih-Tang Sah, “A new semiconductor tetrode, the surface-potential controlled transistor,” Proc. IRE, vol. 49(11), pp. 1623-1634, November 1961.
-
(1961)
Proc. IRE
, vol.49
, Issue.11
, pp. 1623-1634
-
-
Sah, C.-T.1
-
55
-
-
84918052986
-
Effect of surface recombination and channel on p-n junction and transistor characteristics
-
“Effect of surface recombination and channel on p-n junction and transistor characteristics,” IEEE Trans. Electron Devices, vol. 9, no. 1, pp. 94-108, January 1962.
-
(1962)
IEEE Trans. Electron Devices
, vol.9
, Issue.1
, pp. 94-108
-
-
-
56
-
-
84945713471
-
Hot-electron induced mosfet degradation - model, monitor and improvement
-
C. Hu, S. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Kyle, “Hot-electron induced MOSFET degradation - Model, monitor and improvement,” IEEE Trans. Electon Devices, vol. 32, pp. 375-385, 1985.
-
(1985)
IEEE Trans. Electon Devices
, vol.32
, pp. 375-385
-
-
Hu, C.1
Tam, S.2
Hsu, F.C.3
Ko, P.K.4
Chan, T.Y.5
Kyle, K.W.6
-
58
-
-
0023542548
-
The impact of gate-induced drain leakage current on mosfet scaling
-
T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” Tech. Dig. Of IEDM, pp. 718 -721, 1987.
-
(1987)
Tech. Dig. Of IEDM
-
-
Chan, T.Y.1
Chen, J.2
Ko, P.K.3
Hu, C.4
-
59
-
-
0018027059
-
A charge-orient model for mos transistor capacitances
-
D. E. Ward, and R. W. Dutton, “A charge-orient model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. 13, pp. 703-708, 1978.
-
(1978)
IEEE J. Solid-State Circuits
, vol.13
, pp. 703-708
-
-
Ward, D.E.1
Dutton, R.W.2
-
60
-
-
84930093354
-
Capacitance modeling for mosfet
-
Edited by A. E. Ruehli. Amsterdam, The Netherlands: North Holland
-
P. Yang, “Capacitance Modeling for MOSFET,” in Advances in CAD for VLSI, vol. 3, Edited by A. E. Ruehli. Amsterdam, The Netherlands: North Holland, pp. 107-130, 1986.
-
(1986)
Advances in CAD for VLSI
, vol.3
, pp. 107-130
-
-
Yang, P.1
-
61
-
-
85115968795
-
Mosfet intrinsic-capacitance related inaccuracy in cmos circuit speed simulation
-
Virginia
-
Weidong Liu, Michael Orshansky, Xiaodong Jin, Kai Chen, and Chenming Hu, “MOSFET intrinsic-capacitance related inaccuracy in CMOS circuit speed simulation,” IEEE 1997 International Semiconductor Device Research Symposium, pp. 337-340, Virginia, 1997.
-
(1997)
IEEE 1997 International Semiconductor Device Research Symposium
, pp. 337-340
-
-
Liu, W.1
Orshansky, M.2
Jin, X.3
Chen, K.4
Chenming, H.5
-
62
-
-
85115942921
-
Bsim3v3 mosfet model
-
edited by Michael S. Shur and Tor A. Fjeldly, ISBN: 981-02-4280-8, World Scientific
-
Weidong Liu, and Chenming Hu, “BSIM3v3 MOSFET Model” - Silicon and Beyond: Advanced Device Models and Circuit Simulators, edited by Michael S. Shur and Tor A. Fjeldly, pp. 1-31, ISBN: 981-02-4280-8, World Scientific, 2000.
-
(2000)
Silicon and Beyond: Advanced Device Models and Circuit Simulators
, pp. 1-31
-
-
Liu, W.1
Chenming, H.2
-
63
-
-
0032625531
-
An efficient and accurate compact model for thin-oxide-mosfet intrinsic capacitance considering the finite charge thickness for circuit simulation
-
Weidong Liu, Xiaodong Jin, Yachin King, and Chenming Hu, “An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge thickness for circuit simulation,” IEEE Trans. on Electronic Devices, pp.1070-1072, May 1999.
-
(1999)
IEEE Trans. On Electronic Devices
, pp. 1070-1072
-
-
Liu, W.1
Jin, X.2
King, Y.3
Chenming, H.4
-
64
-
-
0003906956
-
-
Memorandum No. UCB/ERL M98/51. Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August 21, . Give total number of pages
-
Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K. Ko, and Chenming Hu, “BSIM3v3.2 MOSFET model - Users’ manual”, Memorandum No. UCB/ERL M98/51. Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August 21, 1998. Give total number of pages.
-
(1998)
Bsim3v3.2 MOSFET Model - Users’ Manual
-
-
Liu, W.1
Jin, X.2
Chen, J.3
Jeng, M.-C.4
Liu, Z.5
Cheng, Y.6
Chen, K.7
Chan, M.8
Hui, K.9
Huang, J.10
Robert, T.11
Ko, P.K.12
Chenming, H.13
-
65
-
-
0003906956
-
-
Memorandum No. UCB/ERL M00/38, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August 3, . Give total number of pages
-
Weidong Liu, Xiaodong Jin, Kanyu M. Cao, and Chenming Hu, “BSIM4.0.0 MOSFET Model - User’s Manual”, Memorandum No. UCB/ERL M00/38, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August 3, 2000. Give total number of pages
-
(2000)
BSIM4.0.0 MOSFET Model - User’s Manual
-
-
Liu, W.1
Jin, X.2
Cao, K.M.3
Chenming, H.4
-
66
-
-
3042510837
-
-
University of California, Berkeley
-
Mohan V. Dunga, Wenwei Morgan Yang, Xuemei Jane Xi, Jin He, Weidong Liu, Kanyu, M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun Chan, Ali M. Niknejad, and Chenming Hu, “BSIM4.6.1 MOSFET Model - User’s Manual,” University of California, Berkeley, 2007.
-
(2007)
BSIM4.6.1 MOSFET Model - Users Manual
-
-
Dunga, M.V.1
Yang, W.M.2
Xi, X.J.3
He, J.4
Liu, W.5
Kanyu, M.C.6
Jin, X.7
Jeff, J.O.8
Chan, M.9
Niknejad, A.M.10
Chenming, H.11
-
67
-
-
0030702636
-
Ac charge centroid model for quantization of inversion layer in nmosfet
-
Taipei, Taiwan
-
Ya-Chin King, H. Fujioka, S. Kamohara, W.-C. Lee, and Chenming Hu, “AC charge centroid model for quantization of inversion layer in NMOSFET,” Int. Symp. VLSI Technology, Systems and Applications, Proc. Of Tech. Papers, Taipei, Taiwan, pp. 245-249, June 1997.
-
(1997)
Int. Symp. VLSI Technology, Systems And Applications, Proc. Of Tech. Papers
, pp. 245-249
-
-
King, Y.-C.1
Fujioka, H.2
Kamohara, S.3
Lee, W.-C.4
Chenming, H.5
-
68
-
-
0032277985
-
An effective gate resistance model for cmos rf and noise modeling
-
San Francisco, December
-
Xiaodong Jin, Jia-Jiunn Ou, Chih-Hung Chen, Weidong Liu, M. Jamal Deen, Paul R. Gray, and Chenming Hu, “An effective gate resistance model for CMOS RF and noise modeling,” Tech. Dig. Of IEDM, pp. 961-964, San Francisco, December 1998.
-
(1998)
Tech. Dig. Of IEDM
, pp. 961-964
-
-
Jin, X.1
Jia-Jiunn, O.2
Chen, C.-H.3
Liu, W.4
Jamal Deen, M.5
Gray, P.R.6
Chenming, H.7
-
69
-
-
0033697178
-
An accurate non-quasi-static mosfet model for simulation of rf and high speed circuits
-
Xiaodong Jin, Kanyu Cao, Jia-Jiunn Ou, Weidong Liu, Yuhua Cheng, Mishel Matloubian, and Chenming Hu, “An accurate non-quasi-static MOSFET model for simulation of RF and high speed circuits,” VLSl Technology, Dig. Of Technical Papers, pp. 196-197, 2000.
-
(2000)
Vlsl Technology, Dig. Of Technical Papers
, pp. 196-197
-
-
Jin, X.1
Cao, K.2
Jia-Jiunn, O.3
Liu, W.4
Cheng, Y.5
Matloubian, M.6
Chenming, H.7
-
70
-
-
0031630376
-
Cmos rf modeling for ghz communication ics,”
-
Jia-Jiunn Ou, Xiaodong Jin, Ingrid Ma, Chenming Hu, and Paul R. Gray, “CMOS RF modeling for GHz communication IC’s,” VLSl Technology, Dig. Of Technical Papers, pp. 94-95, 1998.
-
(1998)
Vlsl Technology, Dig. Of Technical Papers
, pp. 94-95
-
-
Jia-Jiunn, O.1
Jin, X.2
Ma, I.3
Chenming, H.4
Gray, P.R.5
-
71
-
-
84886447987
-
R.F. Mosfet modeling accounting for distributed substrate and channel resistances with emphasis on the bsim3v3 spice model
-
Washington D. C., December
-
W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal, and J.P. Mattia, “R.F. MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model,” Tech. Dig. Of IEDM, pp. 309-312, Washington D. C., December 1997.
-
(1997)
Tech. Dig. Of IEDM
, pp. 309-312
-
-
Liu, W.1
Gharpurey, R.2
Chang, M.C.3
Erdogan, U.4
Aggarwal, R.5
Mattia, J.P.6
-
72
-
-
0026679924
-
An improved deembedding technique for on-wafer high-frequency characterization
-
M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, “An improved deembedding technique for on-wafer high-frequency characterization,” IEEE Proc. Bipolar Circuit and Technology Meeting, pp. 188-191, 1991.
-
(1991)
IEEE Proc. Bipolar Circuit and Technology Meeting
, pp. 188-191
-
-
Koolen, M.C.A.M.1
Geelen, J.A.M.2
Versleijen, M.P.J.G.3
-
74
-
-
0025383482
-
Random telegraph noise of deep-submicrometer mosfets,”
-
K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “Random telegraph noise of deep-submicrometer MOSFET’s,” IEEE Electron Device Letters, vol. 11, no. 2. February 1990.
-
(1990)
IEEE Electron Device Letters
, vol.11
, Issue.2
-
-
Hung, K.K.1
Ko, P.K.2
Hu, C.3
Cheng, Y.C.4
-
75
-
-
0031147079
-
A 1.5 v 1.5ghz cmos low noise amplifier
-
D. K. Shaeffer, and T. H. Lee, “A 1.5 V 1.5GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 745-759
-
-
Shaeffer, D.K.1
Lee, T.H.2
-
76
-
-
0003915801
-
-
Memorandum No. UCB/ERL-M520, Electronics Research Laboratory, College of Engineering, University of California, Berkeley
-
L. W. Nagel, “SPICE2: A Computer Program to Simulate Semiconductor Circuits,” Memorandum No. UCB/ERL-M520, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, May 1975.
-
(1975)
SPICE2: A Computer Program to Simulate Semiconductor Circuits
-
-
Nagel, L.W.1
-
77
-
-
0003490773
-
The spice3 implementation guide, memorandum no
-
Electronics Research Laboratory, College of Engineering, University of California, Berkeley, April 24
-
Thomas L. Quarles, “The SPICE3 Implementation Guide,” Memorandum No. UCB/ERL-M89/44, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, April 24, 1989.
-
(1989)
UCB/ERL-M89/44
-
-
Quarles, T.L.1
-
78
-
-
0003415242
-
-
Memorandum No. UCB/ERL-M89/42, Electronics Research Laboratory, College of Engineering, University of California, Berkeley
-
Thomas L. Quarles, “Analysis of Performance and Convergence Issues for Circuit Simulation,” Memorandum No. UCB/ERL-M89/42, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, April 1989.
-
(1989)
Analysis of Performance and Convergence Issues for Circuit Simulation
-
-
Quarles, T.L.1
-
79
-
-
85115913322
-
Adding devices to spice3, memorandum no
-
College of Engineering, University of California, Berkeley, April 24
-
Thomas L. Quarles, “Adding Devices to SPICE3,” Memorandum No. UCB/ERL-M89/45, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, April 24, 1989.
-
(1989)
UCB/ERL-M89/45, Electronics Research Laboratory
-
-
Quarles, T.L.1
-
80
-
-
85115942921
-
Bsim3v3 mosfet model
-
edited by Michael S. Shur and Tor A. Fjeldly, ISBN: 981-02-4280-8, World Scientific
-
Weidong Liu, and Chenming Hu, “BSIM3v3 MOSFET Model” - Silicon and Beyond: Advanced Device Models and Circuit Simulators, edited by Michael S. Shur and Tor A. Fjeldly, pp. 1-31, ISBN: 981-02-4280-8, World Scientific, 2000.
-
(2000)
Silicon and Beyond: Advanced Device Models and Circuit Simulators
, pp. 1-31
-
-
Liu, W.1
Chenming, H.2
-
81
-
-
0003906956
-
Bsim3v3.2 mosfet model - users manual,”
-
Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August 21
-
Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K. Ko, and Chenming Hu, “BSIM3v3.2 MOSFET model - Users’ manual,” Memorandum No. UCB/ERL M98/51. Electronics Research Laboratory, College of Engineering, University of California, Berkeley, August 21, 1998.
-
(1998)
Memorandum No. UCB/ERL M98/51
-
-
Liu, W.1
Jin, X.2
Chen, J.3
Jeng, M.-C.4
Liu, Z.5
Cheng, Y.6
Chen, K.7
Chan, M.8
Hui, K.9
Huang, J.10
Robert, T.11
Ko, P.K.12
Chenming, H.13
-
82
-
-
0025434759
-
A physics-based mosfet noise model for circuit simulators
-
K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A physics-based MOSFET noise model for circuit simulators,” IEEE Trans. Electron Devices, vol. 37, no. 5. May 1990.
-
(1990)
IEEE Trans. Electron Devices, Vol
, vol.5
, pp. 37
-
-
Hung, K.K.1
Ko, P.K.2
Hu, C.3
Cheng, Y.C.4
-
84
-
-
0034993024
-
A general noise and s-parameter de-embedding procedure for on-wafer high-frequency noise measurements of mosfets
-
C. H. Chen, and M. J. Deen, “A general noise and S-parameter de-embedding procedure for on-wafer high-frequency noise measurements of MOSFETs,” IEEE Trans. on Microwave Theory and Techniques, vol. 49, no.5, pp. 1004-1005, May 2001.
-
(2001)
IEEE Trans. On Microwave Theory and Techniques
, vol.49
, Issue.5
, pp. 1004-1005
-
-
Chen, C.H.1
Deen, M.J.2
-
85
-
-
0033879027
-
Mos transistor modeling for rf ic design
-
C. Enz, and Y. Cheng, “MOS transistor modeling for RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 186-201, Feb. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 186-201
-
-
Enz, C.1
Cheng, Y.2
-
86
-
-
84918044850
-
Theory of low-frequency noise in junction-gate field-effect transistors
-
Chih-Tang Sah, “Theory of low-frequency noise in junction-gate field-effect transistors,” IEEE Transaction on Electron Devices, 11(7), 324-345, July 1964.
-
(1964)
IEEE Transaction on Electron Devices
, vol.11
, Issue.7
, pp. 324-345
-
-
Sah, C.-T.1
-
87
-
-
84930556245
-
The effects of fixed bulk charge on the thermal noise in mos transistors
-
C. T. Sah, S. W. Wu and F. H. Hielscher, “The effects of fixed bulk charge on the thermal noise in MOS transistors,” IEEE Trans. Electron Devices, 13(4), 416-420, April 1966.
-
(1966)
IEEE Trans. Electron Devices
, vol.13
, Issue.4
, pp. 416-420
-
-
Sah, C.T.1
Wu, S.W.2
Hielscher, F.H.3
-
88
-
-
0000269527
-
Evidence of the surface origin of the 1/f noise
-
31 October
-
Chih-Tang Sah and Frank H. Hielscher, “Evidence of the surface origin of the 1/f noise,” Physical Review Letters, 17(18), 956-958, 31 October 1966.
-
(1966)
Physical Review Letters
, vol.17
, Issue.18
, pp. 956-958
-
-
Sah, C.-T.1
Hielscher, F.H.2
-
89
-
-
84916435792
-
Theory and experiments of low-frequency generation-recombination noise in mos transistors
-
Leopaldo D. Yau and Chih-Tang Sah, “Theory and experiments of low-frequency generation-recombination noise in MOS transistors,” IEEE Trans. Electron Devices, 16(2), 170-177, February 1969.
-
(1969)
IEEE Trans. Electron Devices
, vol.16
, Issue.2
, pp. 170-177
-
-
Yau, L.D.1
Sah, C.-T.2
-
90
-
-
0014552486
-
Lumped model analysis of the low-frequency generation noise in gold-doped silicon junction-gate field-effect transistors
-
H. S. Fu and C. T. Sah, “Lumped model analysis of the low-frequency generation noise in gold-doped silicon junction-gate field-effect transistors,” Solid-State Electronics, 12(4), 605-618, April 1969.
-
(1969)
Solid-State Electronics
, vol.12
, Issue.4
, pp. 605-618
-
-
Fu, H.S.1
Sah, C.T.2
-
91
-
-
0014505437
-
Observation of the ideal generation-recombination noise spectrum and spectra with voltage variable relaxation time in gold-doped silicon
-
1 May
-
L. D. Yau and C. T. Sah, “Observation of the ideal generation-recombination noise spectrum and spectra with voltage variable relaxation time in gold-doped silicon,” Applied Physics Letters, 14, 267-269, 1 May 1969.
-
(1969)
Applied Physics Letters
, vol.14
, pp. 267-269
-
-
Yau, L.D.1
Sah, C.T.2
-
92
-
-
0014601002
-
Geometrical dependences of the generation-recombination noise in gold-doped silicon mos transistors
-
L. D. Yau and C. T. Sah, “Geometrical dependences of the generation-recombination noise in gold-doped silicon MOS transistors,” Solid-State Electronics, 12(11), 903-905, November 1969.
-
(1969)
Solid-State Electronics
, vol.12
, Issue.11
, pp. 903-905
-
-
Yau, L.D.1
Sah, C.T.2
-
93
-
-
0347515400
-
On the excess white noise in mos transistors
-
L. D. Yau and C. T. Sah, “On the excess white noise in MOS transistors,” Solid-State Electronics, 12(12), 927-936, December 1969.
-
(1969)
Solid-State Electronics
, vol.12
, Issue.12
, pp. 927-936
-
-
Yau, L.D.1
Sah, C.T.2
-
94
-
-
0346195730
-
Temperature and field dependences of the generation-recombination noise and thermal emission rates at the gold acceptor center in silicon
-
L. D. Yau and C. T. Sah, “Temperature and field dependences of the generation-recombination noise and thermal emission rates at the gold acceptor center in silicon,” Solid-State Electronics 13(9), 1213-1218, September 1970.
-
(1970)
Solid-State Electronics
, vol.13
, Issue.9
, pp. 1213-1218
-
-
Yau, L.D.1
Sah, C.T.2
-
95
-
-
84983900182
-
Equivalent circuit models in semiconductor transport for thermal, optical, auger-impact and tunneling recombination-generation-trapping processes
-
Chih-Tang Sah, “Equivalent circuit models in semiconductor transport for thermal, optical, Auger-impact and tunneling recombination-generation-trapping processes,” Physica Status Solidi, (a)7, 541-559, 16 October 1971.
-
(1971)
Physica Status Solidi
, vol.16
, pp. 541-559
-
-
Sah, C.-T.1
-
96
-
-
0015299686
-
Theory and experiments on surface 1/f noise
-
H. S. Fu and C. T. Sah, “Theory and experiments on surface 1/f noise,” IEEE Transaction on Electron Devices, 19(2), 273-285, February 1972.
-
(1972)
IEEE Transaction on Electron Devices
, vol.19
, Issue.2
, pp. 273-285
-
-
Fu, H.S.1
Sah, C.T.2
-
98
-
-
0004032396
-
-
Section 536, World Scientific Publishing Co,, Singapore
-
Chih-Tang Sah, “Fundamentals of Solid-State Electronics,” Section 536, pp. 441-450, World Scientific Publishing Co,, Singapore, 1991.
-
(1991)
Fundamentals of Solid-State Electronics
, pp. 441-450
-
-
Sah, C.-T.1
-
100
-
-
0003906956
-
Bsim4.0.0 mosfet model - users manual,”
-
Electronics Research Laboratory, College of Engineering, University of California, Berkeley. August 3
-
Weidong Liu, Xiaodong Jin, Kanyu M. Cao, and Chenming Hu, “BSIM4.0.0 MOSFET model - User’s manual,” Memorandum No. UCB/ERL M00/38, Electronics Research Laboratory, College of Engineering, University of California, Berkeley. August 3, 2000.
-
(2000)
Memorandum No. UCB/ERL M00/38
-
-
Liu, W.1
Jin, X.2
Cao, K.M.3
Chenming, H.4
-
101
-
-
0003915801
-
Spice2: A computer program to simulate semiconductor circuits
-
L. W. Nagel, “SPICE2: A Computer Program to Simulate Semiconductor Circuits,” Electronics Research Laboratory, College of Engineering, University of California, Berkeley, Memo No. UCB/ERL-M520, May 1975.
-
(1975)
Electronics Research Laboratory, College of Engineering, University of California, Berkeley, Memo No. UCB/ERL-M520
-
-
Nagel, L.W.1
-
102
-
-
0003490773
-
The spice3 implementation guide
-
College of Engineering, University of California, Berkeley, Memo No. UCB/ERL-M89/44, April 24
-
Thomas L. Quarles, “The SPICE3 Implementation Guide,” Electronics Research Laboratory, College of Engineering, University of California, Berkeley, Memo No. UCB/ERL-M89/44, April 24, 1989.
-
(1989)
Electronics Research Laboratory
-
-
Quarles, T.L.1
-
103
-
-
0003415242
-
Analysis of performance and convergence issues for circuit simulation
-
University of California, Berkeley, Memo No. UCB/ERL-M89/42
-
Thomas L. Quarles, “Analysis of Performance and Convergence Issues for Circuit Simulation,” Electronics Research Laboratory, College of Engineering, University of California, Berkeley, Memo No. UCB/ERL-M89/42, April 1989.
-
(1989)
Electronics Research Laboratory, College of Engineering
-
-
Quarles, T.L.1
-
104
-
-
85115985742
-
Adding devices to spice3, electronics research laboratory, college of engineering, university of california, berkeley, memo no
-
April 24
-
Thomas L. Quarles, “Adding Devices to SPICE3,” Electronics Research Laboratory, College of Engineering, University of California, Berkeley, Memo No. UCB/ERL-M89/45, April 24, 1989.
-
(1989)
UCB/ERL-M89/45
-
-
Quarles, T.L.1
-
106
-
-
85115926389
-
Computation methods for circuit analysis and simulation
-
EE 537 course notes
-
Andrew Yang, “Computation Methods for Circuit Analysis and Simulation,” University of Washington, EE 537 course notes, 1992.
-
(1992)
University of Washington
-
-
Yang, A.1
-
107
-
-
0031122158
-
Cmos scaling into the nanometer regime
-
Y. Taur, D. A. Buchanan, Wei Chen, D. J. Frank, K. E. Ismail, Shih-Hsien Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind, and Hon-Sum Wong, “CMOS scaling into the nanometer regime,” Proceedings of IEEE, vol. 85, pp. 486-504, April 1997.
-
(1997)
Proceedings of IEEE
, vol.85
, pp. 486-504
-
-
Taur, Y.1
Buchanan, D.A.2
Chen, W.3
Frank, D.J.4
Ismail, K.E.5
Lo, S.-H.6
Sai-Halasz, G.A.7
Viswanathan, R.G.8
Wann, H.-J.C.9
Wind, S.J.10
Wong, H.-S.11
-
108
-
-
33646900503
-
Device scaling limits of si mosfets and their application dependencies
-
D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S.P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proceedings of IEEE, vol. 89, pp. 259-288, March 2001.
-
(2001)
Proceedings of IEEE
, vol.89
, pp. 259-288
-
-
Frank, D.J.1
Dennard, R.H.2
Nowak, E.3
Solomon, P.M.4
Taur, Y.5
Wong, H.-S.P.6
-
109
-
-
29044440093
-
Finfet - a self-aligned double gate mosfet scalable to 20nm
-
D. Hisamoto, Wen-Chin Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, Tsu-Jae King, J. Bokor, and Chenming Hu, “FinFET - A self-aligned double gate MOSFET scalable to 20nm,” IEEE Trans. Electron Devices, vol. 47, pp. 2320-2325, December 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.-J.8
Bokor, J.9
Chenming, H.10
-
110
-
-
0032284102
-
Device design considerations for double-gate, ground plane and single-gate ultra-thin soi mosfets at the 25nm channel length generation
-
San Francisco, December
-
H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design considerations for double-gate, ground plane and single-gate ultra-thin SOI MOSFETs at the 25nm channel length generation,” IEDM Tech. Dig., pp. 407-410, San Francisco, December 1998.
-
(1998)
IEDM Tech. Dig
, pp. 407-410
-
-
Wong, H.-S.P.1
Frank, D.J.2
Solomon, P.M.3
-
111
-
-
4243799729
-
K, v. Subramanian, tsu-jae king, j. Bokor, and chenming hu, sub-50 nm finfet: Pmos
-
Washington D. C., December
-
Xuejue Huang, Wen-Chin Lee, Charles Kuo, D. Hisamoto, Leland Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Yang-Kyu Choi, K. Asano, K, V. Subramanian, Tsu-Jae King, J. Bokor, and Chenming Hu, ”Sub-50 nm FinFET: PMOS ”, Tech. Dig. Of IEDM, pp. 67-70, Washington D. C., December 1999.
-
(1999)
Tech. Dig. Of IEDM
, pp. 67-70
-
-
Huang, X.1
Lee, W.-C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
Anderson, E.7
Takeuchi, H.8
Choi, Y.-K.9
Asano, K.10
-
112
-
-
0035694506
-
Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate mosfets
-
Y. Taur, “Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 48, pp. 2861-2869, December 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 2861-2869
-
-
Taur, Y.1
-
113
-
-
46049118238
-
Psp-based compact finfet model describing dc and rf measurements
-
San Francisco, December
-
G. D. J. Smit, A. J. Scholten, N. Serra, R. M. T. Pijper, R. van Langevelde, A. Mercha, G. Gildenblat, and D. B. M. Klassen, “PSP-based compact FinFET model describing dc and RF measurements,” IEDM Tech. Dig., pp. 175-178, San Francisco, December 2006.
-
(2006)
IEDM Tech. Dig
, pp. 175-178
-
-
Smit, G.D.J.1
Scholten, A.J.2
Serra, N.3
Pijper, R.M.T.4
Van Langevelde, R.5
Mercha, A.6
Gildenblat, G.7
Klassen, D.B.M.8
-
114
-
-
85115920108
-
Bsim-cmg: A compact model for multi-gate transistors, chapter 3 in finfets and other multi-gate transistors
-
New York, NY
-
M. V. Dunga, C-H. Lin, A. Niknejad, and C. Hu, “BSIM-CMG: A Compact Model for Multi-Gate Transistors,” Chapter 3 in FinFETs and Other Multi-Gate Transistors, J. P. Colinge, Edited, Springer Science, New York, NY, pp. 113-153, 2007.
-
(2007)
J. P. Colinge, Edited, Springer Science
, pp. 113-153
-
-
Dunga, M.V.1
Lin, C.-H.2
Niknejad, A.3
Hu, C.4
-
115
-
-
38649083893
-
Bsim-mg: A versatile multi-gate fet model for mixed-signal design
-
Mohan V. Dunga, Chung-Hsun Lin, Darsen D. Lu, Weize Xiong, C. R. Cleavelin, P. Patruno, Jiunn-Ren Hwang, Fu-Liang Yang, Ali M. Niknejad, and Chenming Hu, “BSIM-MG: A versatile multi-gate FET model for mixed-signal design,” Proceedings of the VLSI Technology Symposium, pp. 80-81, 2007.
-
(2007)
Proceedings of the VLSI Technology Symposium
, pp. 80-81
-
-
Dunga, M.V.1
Lin, C.-H.2
Darsen, D.L.3
Xiong, W.4
Cleavelin, C.R.5
Patruno, P.6
Hwang, J.-R.7
Yang, F.-L.8
Niknejad, A.M.9
Chenming, H.10
-
116
-
-
0017932965
-
A charge sheet model of the mosfet
-
J. R. Brews, “A charge sheet model of the MOSFET,” Solid-State Electronics, vol. 21, pp. 345-355, 1978.
-
(1978)
Solid-State Electronics
, vol.21
, pp. 345-355
-
-
Brews, J.R.1
-
117
-
-
0018027059
-
A charge-oriented model for mos transistor capacitances
-
D. Ward, and R. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid State Circuits, vol. SSC-13, pp. 703-708, October 1978
-
(1978)
IEEE J. Solid State Circuits
, vol.SSC-13
, pp. 703-708
-
-
Ward, D.1
Dutton, R.2
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