Mosfet carrier mobility model based on gate oxide thickness, threshold and gate voltages

Solid-State Electronics

Volumn 39, Issue 10, 1996, Pages 1515-1518

  Chen, Kai ^a   Clement Wann, H ^a   Dunster, Jon ^a   Ko, Ping K ^a   Hu, Chenming ^a   Yoshida, Makoto ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; CAPACITANCE; ELECTRIC FIELD EFFECTS; ELECTRON ENERGY LEVELS; GATES (TRANSISTOR); ION IMPLANTATION; MATHEMATICAL MODELS; MOSFET DEVICES; OXIDES; SEMICONDUCTOR DOPING; SURFACES;

GATE OXIDE THICKNESS; GATE VOLTAGE; MOSFET CARRIER MOBILITY; THRESHOLD VOLTAGE;

ELECTRON TRANSPORT PROPERTIES;

EID: 0030269375     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(96)00059-7     Document Type: Article

References (4)

1. A. G. Sabnis and J. T. Clemens, IEDM Tech. Digest 18 (1979).
2. M. S. Liang, J. Y. Choi, P. K. Ko and C. Hu, IEEE Trans. Electron Devices ED-33, 409 (1986).
3. S. Takagi, A. Toriumi, M. Isase and H. Tango, IEEE Trans. Electron Devices 41, 2357 (1994).
4. K. Lee, J. Choi, S. Sim and C. Kim, IEEE Trans. Electron Devices 38, (1991).