Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs

Solid-State Electronics

Volumn 48, Issue 6, 2004, Pages 969-978

  Chan, Mansun ^a   Su, Pin ^b   Wan, Hui ^c   Lin, Chung Hsun ^c   Fung, Samuel K H ^d   Niknejad, Ali M ^c   Hu, Chenming ^c   Ko, Ping K ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

BSIMSOI; Circuit simulation; Device model; SOI; SOI devices; SPICE

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); IMPACT IONIZATION; SILICON ON INSULATOR TECHNOLOGY;

BSIMSOI; CIRCUIT SIMULATION; DEVICE MODEL; SOI DEVICES; SPICE;

MOSFET DEVICES;

EID: 1442336332     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.12.012     Document Type: Article

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