The Analysis of System-Level Timing Failures Due to Interconnect Reliability Degradation

IEEE Transactions on Device and Materials Reliability

Volumn 8, Issue 4, 2008, Pages 652-663

  Guo, Jin ^a   Papanikolaou, Antonis ^b   Stucchi, Michele ^a   Croes, Kristof ^a   Tokei, Zsolt ^a   catthoor, Francky ^c  

^a IMEC   (Belgium)

^b NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Electromigration (EM); interconnect reliability; system level analysis; time dependent dielectric breakdown (TDDB)

Indexed keywords

EID: 85008013667     PISSN: 15304388     EISSN: 15582574     Source Type: Journal    
DOI: 10.1109/TDMR.2008.2006986     Document Type: Article

References (40)

1. International Technology Roadmap for Semiconductors 2007 Edition. [2] A. Papanikolaou, “Reliability issues in deep deep sub-micron technologies: Time-dependent variability and its impact on embedded system design,” in Proc. IFIP Int. Conf. VLSI-SoC, 2006, pp. 342–347.
2. J. McPherson, “Reliability trends with advanced CMOS scaling and the implications for design,” in Proc. CICC, 2007, pp. 405–412.
3. A. B. Kahng and Y. C. Pati, “Subwavelength optical lithography: Challenges and impact on physical design,” in Proc. ISPD, 1999, pp. 112–119.
4. T. Serdar, O. Omedes, and B. Carpentier, “Timing preservation in wire spreading utilized for yield improvement,” in Proc. ICICDT, 2006, pp. 1–4.
5. K.-Y. Lee, T.-C. Wang, and K.-Y. Chao, “Post-routing redundant via insertion and line end extension with via density consideration,” in Proc. IEEE/ACM Int. Conf. Comvut.-Aided Des. 2006, pp. 633–640.
6. C. Guardiani, M. Bertoietti, N. Dragone, M. Malcotti, and P. McNamara, “An effective DFM strategy requires accurate process and IP pre-characterization in Proc. DAC, 2005, pp. 13–17.
7. G. Groeseneken, R. Degraeve, B. Kaczer, and P. Roussel, “Recent trends in reliability assessment of advanced CMOS technologies,” in Proc. Int. Conf. Microelectron. Test Struct., 2005, pp. 81–88.
8. V. Reddy, A. Krishnan, A. Marshall et al., “Impact of negative bias temperature instability on digital circuit reliability,” in Proc. IRPS, 2002, pp. 248–254.
9. C. Bruynseraede, F. Tokei, Z. Iacopi, G. Beyer, J. Michelon, and K. Maex, “The impact of scaling on interconnect reliability,” in Proc. IEEE Int. Reliab. Phys. Symp., 2005, pp. 7–17.
10. Z. Tokei, Y. Li, and G. Beyera, “Reliability challenges for copper low-k dielectrics and copper diffusion barriers,” Microelectron. Reliab., vol. 45, no. 9-11, pp. 1436–1442, Sep./Nov. 2005.
11. Primetime Tutorial, Synopsys, Mountain View, CA, 2005.
12. Encounter User Guide, Cadence Design Syst., San Jose, CA, Jul. 2006.
13. R. Tu, “Berkeley reliability tools—BERT,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 10, pp. 1524–1534, Oct. 1993.
14. J. Hall, D. Hocevar, P. Yang, and M. McGraw, “SPIDER—A CAD system for modeling VLSI metallization patterns,” IEEE Trans. Comput. - Aided Design Integr. Circuits Syst., vol. CAD-6, no. 6, pp. 1023–1031, Apr. 1987.
15. D. Frost and K. Poole, “RELIANT: A reliability analysis tool for VLSI interconnect,” IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 458–462, Apr. 1989.
16. T. Simunic, K. Mihic, and G. De Micheli, “Optimization of reliability and power consumption in systems on a chip,” in Proc. PATMOS, 2005, pp. 237–246.
17. A. K. Coskun, T. S. Rosing, Y. Leblebici, and G. D. Micheli, A simulation methodology for reliability analysis in multi-core SOCs,” in Proc. GLSVLSI, 2006, pp. 95–99.
18. J. Shin, V. Zyuban, Z. Hu, J. A. Rivers, and P. Bose, “A framework for architecture-level lifetime reliability modeling,” in Proc. IEEE/IFIP Int. Conf. DSN, 2007, pp. 534–543.
19. X. Xuan, A. Chatterjee, and A. Singh, “ARET for system-level IC reliability simulation,” in Proc. IEEE IRPS, 2003, pp. 572–573.
20. Q. Li, J. Zhang, W. Li et al., “RF circuit performance degradation due to soft breakdown and hotcarrier effect in 0.18 μm CMOS technology,” in Proc. RFIC, 2001, pp. 139–142.
21. H. Wang, M. Miranda, F. Catthoor, and D. Wim, “Impact of random soft oxide breakdown on SRAM energy/delay drift,” IEEE Trans. Device Mater. Rel., vol. 7, no. 4, pp. 581–591, Dec. 2007.
22. Y. Li, G. Groeseneken, K. Maex, and Z. Tokei, “Real-time investigation of conduction mechanism with bias stress in silica-based intermetal dielectrics,” IEEE Trans. Device Mater. Rel., vol. 7, no. 2, pp. 252–258, Jun. 2007.
23. E. Ogawa, K.-D. Lee, V. Blaschke, and P. Ho, “Electromigration reliability issues in dual-damascene Cu interconnections,” IEEE Trans. Rel., vol. 51, no. 4, pp. 403–419, Dec. 2002.
24. C.-K. Hu, L. M. Gignac, E. Liniger et al., “Effect of metal liner on electromigration in Cu damascene lines,” J. Appl. Phys., vol. 98, no. 12, pp. 124 501-1-124 501–8, Dec. 2005.
25. T. Lee, K. Watson, J. Fen Chen et al., “Characterization and reliability of TaN thin film resistors,” in Proc. IRPS, 2004, pp. 502–508.
26. I. A. Blech, “Electromigration in thin aluminum films on titanium nitride,” J. Appl. Phys., vol. 47, no. 4, pp. 1203–1208, Apr. 1976.
27. K.-D. Lee, E. T. Ogawa, H. Matsuhashi et al., “Electromigration critical length effect in Cu/oxide dual-damascene interconnects,” Appl. Phys. Lett., vol. 79, no. 20, pp. 3236–3238, Nov. 2001.
28. C. Hau-Riege, A. Marathe, and V. Pham, “The effect of line length on the electromigration reliability of Cu interconnects,” in Proc. Adv. Metallization Conf, 2002, pp. 169–175.
29. J. R. Black, “Mass transport of aluminum by momentum exchange with conducting electrons,” in Proc. IEEE IRPS, 1967, pp. 148–159.
30. L. Doyen, X. Federspiel, D. Ney et al., “Residual resistivity model and its application,” in Proc. IEEE Int. Integr. Reliab. Workshop Final Rep., 2006, pp. 134–135.
31. B. Li, T. D. Sullivan, T. C. Lee, and D. Badami, “Reliability challenges for copper interconnects,” Microelectron. Reliabil., vol. 44, no. 3, pp. 365–380, Mar. 2003.
32. M. Hussein and J. He, “Materials’ impact on interconnect process technology and reliability,” IEEE Trans. Semicond. Manuf, vol. 18, no. 1, pp. 69–85, Feb. 2005.
33. C.-K. Hu, L. Gignac, and R. Rosenberg, “Electromigration of Cu/low dielectric constant interconnects,” Microelectron. Reliab., vol. 46, no. 2–4, pp. 213–231, Feb.-Apr. 2005.
34. W. Wen, D. Xiaodong, and J. Yuan, “A physical model of time-dependent dielectric breakdown in copper metallization,” in Proc. Reliab. Phys. Symp., 2003, pp. 282–286.
35. W. McPherson and H. Mogul, “Underlying physics of the thermochemical E model in describing low-field time-dependent dielectric breakdown in Si02 thin films,” J. Appl. Phys., vol. 84, no. 3, pp. 1513–1523, Aug. 1998.
36. F. Chen, O. Bravo, K. Chanda et al., “A comprehensive study of low-k SICOH TDDB phenomena and its reliability lifetime model development,” in Proc. IRPS, 2006, pp. 46–53.
37. E. Ogawa, J. Kim, G. Haase et al., “Leakage, breakdown, and TDDB characteristics of porous low-k silica-based interconnect dielectrics,” in Proc. IRPS, 2003, pp. 166–172.
38. Y. Li, “Low-k dielectric reliability in copper interconnects,” Ph.D. dissertation, Katholieke Universiteit Leuven, Leuven, Belgium, Sep. 2007.
39. B. Bougard, D. Naessens, F. Hollevoet et al., “A scalable baseband platform for energy-efficient reactive software-defined-radio,” in Proc. 1st Int. Conf. Cogn. Radio Oriented Wireless Netw. Commun., 2006, pp. 1–5.
40. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New paradigm of predictive MOSFET and interconnect modeling for early circuit design,” in Proc. CICC, 2000, pp. 201–204.