Aret for system-level IC reliability simulation

IEEE International Reliability Physics Symposium Proceedings

Volumn 2003-January, Issue , 2003, Pages 572-573

  Xuan, Xiangdong ^a   Chatterjee, Abhijit ^a   Singh, Adit D ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; DEFECTS;

DESIGN FOR RELIABILITY; FABRICATION DEFECTS; GEORGIA INSTITUTE OF TECHNOLOGY; HIERARCHICAL ANALYSIS; PHYSICAL DEFECTS; RELIABILITY EVALUATION; STATISTICAL APPROACH; SYSTEM LEVEL SIMULATION;

RELIABILITY;

EID: 56749135833     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2003.1197811     Document Type: Conference Paper

References (0)