Timing preservation in wire spreading utilized for yield improvement

2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

Volumn , Issue , 2006, Pages

  Serdar, Tatjana ^a   Omedes, Olivier ^a   Carpentier, Benoit ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC WIRE; TIMING CIRCUITS;

TIMING DEGRADATION; WIRE SPREADING; WIRE WIDENING;

INTEGRATED CIRCUIT LAYOUT;

EID: 37649028991     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2006.220830     Document Type: Conference Paper

References (6)

1. T. Hama, H. Etoh, "Curvilinear Detailed Routing with Simultaneous Wire Spreading and Wire-Fattening", IEEE Transaction on Computer Added Design and IC, Vol. 18, No. 11, Nov. 1999.
2. R. B. Hitchcock, "Timing Verification and the Timing Analysis Program", Proceeding of the DAC, pp 594-604, 1982.
3. G. A. Allan, "Targeted Layout Modifications for Semiconductor Yield/Reliability Enhancement", IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 4, Nov. 2004.
4. H. Youssef, R.-B. Lin, and E. Shragowitz, "Bounds on net delays for VLSI circuits", in IEEE Proc. Of ISCAS, 1992, pp. 815-824.
5. S. L. Lin, and J. Allen, "Minplex - A Compactor that Minimizes the Bounding Rectangle and Individual Rectangles in a Layout", in IEEE Proc. Of DAC, 1986, pp. 123-130.
6. D. M. Walker, "Critical Area Analysis", in Proc. Of IEEE Int. Conf. on Wafer Scale Integration, 1992, pp. 281-290.