Real-time investigation of conduction mechanism with bias stress in silica-based intermetal dielectrics

IEEE Transactions on Device and Materials Reliability

Volumn 7, Issue 2, 2007, Pages 252-258

  Li, Yunlong ^a,b,c   Groeseneken, Guido ^a,b,c   Maex, Karen ^b,c   Tokei, Zsolt ^b  

^a IEEE

^b IMEC   (Belgium)

^c Katholieke Universiteit Leuven   (Belgium)

Author keywords

Bias stress; Conduction mechanism; Interconnect; Low k dielectrics

Indexed keywords

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC MATERIALS; MATHEMATICAL MODELS; SILICA;

BIAS STRESS; CONDUCTION MECHANISM; LOW-K DIELECTRICS;

ELECTRIC CONDUCTIVITY;

EID: 34548217650     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2007.901087     Document Type: Conference Paper

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