A simulation methodology for reliability analysis in multi-core SoCs

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 95-99

  Coskun, Ayse K ^a   Rosing, Tajana Simunic ^a   Leblebici, Yusuf ^b   De Micheli, Giovanni ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b EPFL   (Switzerland)

Author keywords

MP SoC reliability; Reliability modeling; Reliability simulation

Indexed keywords

COMPUTER SIMULATION; RELIABILITY; SYSTEMS ANALYSIS;

RELIABILITY MODELING; RELIABILITY SIMULATION; SOC RELIABILITY;

CHIP SCALE PACKAGES;

EID: 33750919946     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127933     Document Type: Conference Paper

References (21)

1. L. Benini, D. Bertozzi, A. Bogliolo, F. Menichelli, and M. Olivieri. Mparm: Exploring the multi-processor soc design space with systeme. Springer J. of VLSI Signal Processing, 41, no. 2, 2005.
2. L. Benini, A. Bogliolo, and G. D. Micheli. A survey of design techniques for system-level dynamic power management. IEEE Transactions on VLSI, 8, No. 3:299-316, 2000.
3. R. Degraeve and J. O. et. al. A new model for the field dependence of intristic and extrinsic time-dependent dielectric breakdown. IEEE Transactions on Elect. Devices, 45, n.2, Feb 1998.
4. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. Compact thermal modeling for temperature-aware design. In DAC, 2004.
5. Intersil. Thermal design considerations, application note 1096. www.intersil.com.
6. A. Karlin, M. Manesse, L. McGeoch, and S. Owicki. Competitive randomized algorithms for nonuniform problems. Algorithmica, pages 542-571, 1994.
7. W. Kim, D. Shin, H.-S. Yun, J. Kim, and S. L. Min. Performance comparison of dynamic voltage scaling algorithms for hard real-time systems. In IEEE RTAS, 2002.
8. C. Locke, D. Vogel, and T. Mesler. Building a predictable avionics platform in ada: a case study. In IEEE Real-Time Systems Symposium, 1991.
9. H. Nguyen. Multilevel interconnect reliability on the effects of electro-thremomechanical stresses. Ph.D. dissertation, Univ. of Twente, Netherlands, March 2004.
10. P. Pillai and K. G. Shin. Real-time dynamic voltage scaling for low-power embedded operating systems. In SOSP, pages 89-102, 2001.
11. P. Rong and M. Pedram. Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system. In ASPDAC, 2006.
12. Semiconductor device reliability failure models. International Sematech Technology Transfer document 00053955A-XFR, 2000.
13. F. Semiconductor. Heatsink small outline package (hsop), application note 2388. www.freescale.com.
14. T. Simunic, K. Mihic, and G. D. Micheli. Reliability and power management of integrated systems. In DSD, 2004.
15. T. Simunic, K. Mihic, and G. D. Micheli. Optmization of reliability and power consumption in systems on a chip. In PATMOS, 2005.
16. K. Skadron et al. Control-theoretic techniques and thermal-rc modeling for accurate and localized dynamic thermal management. In HPCA, 2002.
17. K. Skadron. Hybrid architectural dynamic thermal management. In DATE, 2004.
18. K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecture. In ISCA, 2003.
19. J. Srinivasan, S. Adve, P. Bose, J. Rivers, and C. Hu. Ramp: A model for reliability aware microprocessor design. IBM Research Report, 2003.
20. J. Srinivasan and S. V. Adve. Predictive dynamic thermal management for multimedia applications. In ICS, 2003.
21. Intel pxa270 processor electrical, mechanical and thermal specification data sheet, www.intel.com.