Optimization of reliability and power consumption in systems on a chip

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3728 LNCS, Issue , 2005, Pages 237-246

  Simunic, Tajana ^a   Mihic, Kresimir ^b   De Micheli, Giovanni ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SYSTEM INTERCONNECTION; ENERGY CONSERVATION; MICROPROCESSOR CHIPS; RELIABILITY; TRANSISTORS;

CHIP DESIGNS; POWER CONSUMPTION; TRANSISTOR SCALING; VOLTAGE MARGINS;

COMPUTER SYSTEMS;

EID: 33646451678     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11556930_25     Document Type: Conference Paper

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