A framework for architecture-level lifetime reliability modeling

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2007, Pages 534-543

  Shin, Jeonghee ^a,b,c   Zyuban, Victor ^a   Hu, Zhigang ^a   Rivers, Jude A ^a   Bose, Pradip ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^c IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP LIFETIME RELIABILITY; ENVIRONMENTAL PARAMETERS; FORC; RELIABILITY MODELING;

CIRCUIT THEORY; COMPUTER ARCHITECTURE; FAILURE ANALYSIS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION;

RELIABILITY ANALYSIS;

EID: 36048997906     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2007.8     Document Type: Conference Paper

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