Reliability issues in deep deep sub-micron technologies: Time-dependent variability and its impact on embedded system design

IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip

Volumn , Issue , 2006, Pages 342-347

  Papanikolaou, Antonis ^a   Miranda, Miguel ^a   Wang, Hua ^a   Catthoor, Francky ^a   Satyakiran, Munaga ^a   Marchai, Pol ^a   Kaczer, Ben ^a   Bruynseraede, Christophe ^a   Tokei, Zsolt ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; ENERGY POLICY; LSI CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEMS ANALYSIS; TECHNOLOGY;

45 NM TECHNOLOGY; DEEP SUB MICRON (DSM) TECHNOLOGIES; EMBEDDED SYSTEM DESIGNS; INTERNATIONAL CONFERENCES; PARADIGM SHIFTS; PROCESS VARIABILITY; QUALITY METRICS; REDUCED ENERGY; SYSTEM LEVELS; SYSTEM ON CHIP (SOCS); SYSTEM-LEVEL DESIGNS; TECHNOLOGY SCALING; TIME-DEPENDENT; VERY LARGE SCALE INTEGRATION (VLSI);

INTEGRATED CIRCUITS;

EID: 46249125523     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2006.313258     Document Type: Conference Paper

References (27)

1. H.Wang et al., "Impact of deep submicron (DSM) process variation effects in SRAM design", DATE 2005.
2. A. Papanikolaou et al., "A System-Level Methodology for Fully Compensating Process Variability Impact of Memory Organizations in Periodic Applications", CODES+ISSS 2005.
3. C. Visweswariah, "Statistical Timing of Digital Integrated Circuits", Microprocessor Circuit Design Forum at ISSCC 2004.
4. G. Groeseneken et al., "Recent trends in reliability assessment of advanced CMOS technologies", ICMTS 2005.
5. B. Kaczer et al., "Understanding nMOSFET characteristics after soft breakdown and their dependence on the breakdown location", ESSDERC 2002.
6. J.R. Carter et al., "Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown", DATE 2005.
7. A. Avellan et al., "Impact of soft and hard breakdown on analog and digital circuits", IEEE Trans. Device and Materials Reliability 2004.
8. R. Rodriguez et al., "Oxide breakdown model and its impact on SRAM cell functionality", SISPAD 2003.
9. B. Kaczer et al., "Experimental verification of SRAM Cell functionality after hard and soft gate oxide breakdowns", ESSDERC 2003.
10. H. Wang et al., "On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components", to appear MTDT 2006.
11. J. Stathis, "Physical and Predictive Models of Ultrathin Oxide Reliability in CMOS Devices and Circuits", IEEE Trans. Device and Materials Reliability, 2001.
12. M. Mani et al., "A new statistical optimization algorithm for gate sizing", ICCD 2004.
13. S. Kumar et al., "Impact of NBTI on SRAM Read Stability and Design for Reliability", ISQED 2006.
14. V. Ramadurai et al., "SRAM operational voltage shifts in the presence of gate oxide defects in 90 nm SOI", IRPS 2006.
15. F. Najm, "On the need for statistical timing analysis", DAC 2005.
16. E. Grossar et al., "Statistically aware SRAM memory array design", ISQED 2006.
17. A.Papanikolaou et al., "A system architecture case study for efficient calibration of memory organizations under process variability", WASP 2005.
18. T. Austin et al., "Making typical silicon matter with Razor", IEEE Computer 2004.
19. C. Bruynseraede et al., "The impact of scaling on interconnect reliability", IRPS 2005.
20. Z. Tokei et al., "Reliability challenges for copper low-k dielectrics and copper diffusion barriers", J. of Microelectronics Reliability 2005.
21. D.Schroder and J.Babcock, "Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing", J.Appl.Phys, vol.94, 2003.
22. V.Reddy et al., "Impact of Negative Bias Temperature Instability on Digital Circuit Reliability", IRPS 2002.
23. J.H.Stathis et.al, "Impact of ultra thin oxide breakdown on circuits", ICICDT 2005.
24. B. Kaczer, et.al, "Implications of progressive wear-out for lifetime extrapolation of ultra-thin SiON films", IEDM 2004.
25. ITRS, www.itrs.net
26. J.A.Croon et al., "Line Edge Roughness: Characterisation, Modelling and Impact on Device Behaviour", IEDM 2002.
27. D. Brahme et al., "Functional testing of microprocessors", IEEE Trans. Computers 1984.