CLEAR: Crosslayer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores

Proceedings - Design Automation Conference

Volumn 05-09-June-2016, Issue , 2016, Pages

  Cheng, Eric ^a   Mirkhani, Shahrzad ^a   Szafaryn, Lukasz G ^b   Cher, Chen Yong ^c   Cho, Hyungmin ^a   Skadron, Kevin ^b   Stan, Mircea R ^b   Lilja, Klas ^d   Abraham, Jacob A ^e   Bose, Pradip ^c   Mitra, Subhasish ^a  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF VIRGINIA   (United States)

^c IBM RESEARCH   (United States)

^d Robust Chip Inc   (United States)

^e UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Cross layer resilience; Soft errors

Indexed keywords

BENCHMARKING; COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; COST EFFECTIVENESS; COSTS; CRIME; DESIGN; ERROR CORRECTION; ERRORS; GENERAL PURPOSE COMPUTERS; HARDENING; INTEGRATED CIRCUIT DESIGN; LOGIC CIRCUITS; MULTIPROCESSING SYSTEMS; RADIATION HARDENING; RECONFIGURABLE HARDWARE; SOFTWARE RELIABILITY; PULSE ANALYZING CIRCUITS;

COST-EFFECTIVE SOLUTIONS; CROSS LAYER; GENERAL PURPOSE PROCESSORS; OUT-OF-ORDER PROCESSORS; SILENT DATA CORRUPTIONS; SINGLE-EVENT MULTIPLE-UPSET; SOFT ERROR; TERRESTRIAL ENVIRONMENTS;

COST BENEFIT ANALYSIS;

EID: 84977070666     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2897937.2897996     Document Type: Conference Paper

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