Assessment of the impact of cosmic-ray-induced neutrons on hardware in the roadrunner supercomputer

IEEE Transactions on Device and Materials Reliability

Volumn 12, Issue 2, 2012, Pages 445-454

  Michalak, Sarah E ^a   DuBois, Andrew J ^a   Storlie, Curtis B ^a   Quinn, Heather M ^a   Rust, William N ^a   DuBois, David H ^a   Modl, David G ^a   Manuzzato, Andrea ^b   Blanchard, Sean P ^a  

^a LOS ALAMOS NATIONAL LABORATORY   (United States)

^b UNIVERSITY OF MILAN   (Italy)

Author keywords

Failures in time (FIT); neutron beam testing; silent data corruption (SDC); single event effect; soft error

Indexed keywords

DATA CORRUPTION; HIGH-PERFORMANCE COMPUTING; RESEARCH QUESTIONS; SINGLE EVENT EFFECTS; SOFT ERROR;

COMPUTER HARDWARE; COMPUTER SOFTWARE SELECTION AND EVALUATION; CRIME; HARDWARE; MICROPROCESSOR CHIPS; NEUTRONS;

SUPERCOMPUTERS;

EID: 84862004001     PISSN: 15304388     EISSN: 15582574     Source Type: Journal    
DOI: 10.1109/TDMR.2012.2192736     Document Type: Article

References (39)

1. R. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 305-316, Sep. 2005.
2. C. Constantinescu, "Neutron SER characterization of microprocessors," in Proc. Int. Conf. Dependable Syst. Netw., 2005, pp. 754-759.
3. S.Michalak, K. Harris, N. Hengartner, B. Takala, and S.Wender, "Predicting the number of fatal soft errors in Los Alamos National Laboratory's ASC Q supercomputer," IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 329-335, Sep. 2005.
4. H. Ando, R. Kan, Y. Tosaka, K. Takahisa, and K. Hatanaka, "Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor," in Proc. IEEE Int. Conf. Dependable Syst. Netw., 2008, pp. 62-69.
5. S. Rao, T. Hong, P. Sanda, J. Ackaret, A. Barrera, J. Yanez, S. Mitra, J. Kellington, and R. McBeth, "Examining workload dependence of soft error rates," in Proc. SELSE, 2008.
6. P. Sanda, J. Kellington, P. Kudva, R. Kalla, R. McBeth, J. Ackaret, R. Lockwood, J. Schumann, and C. Jones, "Soft-error resilience of the IBM POWER6 processor," IBM J. Res. Develop., vol. 52, no. 3, pp. 275-284, 2008.
7. T. Hong, S. Michalak, T. Graves, J. Ackaret, and S. Rao, "Neutron beam irradiation study of workload dependence of SER in a microprocessor," in Proc. SELSE, 2009, pp. 1-5.
8. F. Wrobel, J. Gasiot, and F. Saigne, "Hafnium and uranium contributions to soft error rate at ground level," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3141-3145, Dec. 2008.
9. J. Autran, D. Munteanu, P. Roche, G. Gasiot, S. Martinie, S. Uznanski, S. Sauze, S. Semikh, E. Yakushev, S. Rozov, P. Loaiza, G. Warot, and M. Zampaolo, "Soft-errors induced by terrestrial neutrons and natural alpha-particle emitters in advanced memory circuits at ground level," Microelectron. Reliab., vol. 50, no. 9-11, pp. 1822-1831, 2010.
10. Z. Kalbarczyk, R. Iyer, and L. Wang, "Application fault tolerance with armor middleware," IEEE Internet Comput., vol. 9, no. 2, pp. 28-37, Mar./Apr. 2005.
11. D. Katz, Application-Based Fault Tolerance for Spaceborne Applications. [Online]. Available: http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/10574/1/ 02-2631.pdf
12. K. Koch, Roadrunner Platform Overview, 2008. [Online]. Available: http://www.lanl.gov/orgs/hpc/roadrunner/pdfs/Koch%20-% 20Roadrunner%20Overview/ RR%20Seminar%20-%20System% 20Overview.pdf
13. H. Meuer, 31st TOP500 List Topped by First-Ever Petaflop/s Supercomputer Scientific Computing, 2008. [Online]. Available: http://www.scientificcomputing. com/31st-TOP500-List-Topped-by-Firstever-Petaflops-Supercomputer.aspx
14. C. Storlie, S. Michalak, H. Quinn, A. DuBois, and D. DuBois, "A Bayesian survival analysis of neutron-induced errors in high performance computing hardware," Los Alamos Nat. Lab., Los Alamos, NM, 2011.
15. S. Michalak, A. DuBois, C. Storlie, H. Quinn, W. Rust, D. DuBois, D. Modl, A. Manuzzato, and S. Blanchard, "Neutron beam testing of high performance computing hardware," in Proc. IEEE Nucl. Space Radiation Effects Conf. Radiation Effects Data Workshop, 2011, pp. 1-8.
16. D. Hiemstra, A. Baril, and M. Dettwiler, "Single event upset characterization of the Pentium (R) MMX and Pentium (R) II microprocessors using proton irradiation," IEEE Trans. Nucl. Sci., vol. 46, no. 6, pp. 1453-1460, Dec. 1999.
17. D. Hiemstra and A. Baril, "Single event upset characterization of the Pentium (R) MMX and Celeron (R) microprocessors using proton irradiation," in Proc. IEEE Radiation Effects Data Workshop, 2000, pp. 39-44.
18. D. Hiemstra, S. Yu, and M. Pop, "Single event upset characterization of the Pentium (R) MMX and Low Power Pentium (R) MMX microprocessors using proton irradiation," in Proc. IEEE Radiation Effects Data Workshop, 2001, pp. 32-37.
19. D. Hiemstra, S. Yu, and M. Pop, "Single event upset characterization of the Pentium 4, Pentium III and Low Power Pentium MMX microprocessors using proton irradiation," in Proc. IEEE Radiation Effects Data Workshop, 2002, pp. 51-57.
20. G. Swift, F. Farmanesh, F. Guertin, F. Irom, and D. Millward, "Single-event upset in the PowerPC750 microprocessor," IEEE Trans. Nucl. Sci., vol. 48, no. 6, pp. 1822-1827, Dec. 2001.
21. F. Irom, F. Farmanesh, and C. Kouba, "Single-event upset and scaling trends in new generation of the commercial SOI PowerPC microprocessors," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3563-3568, Dec. 2006.
22. F. Irom, T. Miyahira, D. Nguyen, I. Jun, and E. Normand, "Results of recent 14 MeV neutron single event effects measurements conducted by the Jet Propulsion Laboratory," in Proc. IEEE Radiation Effects Data Workshop, 2007, pp. 141-145.
23. A. Dixit, R. Heald, and A. Wood, "Trends from ten years of soft error experimentation," in Proc. SELSE, 2009, pp. 1-4.
24. A. Dixit and A.Wood, "The impact of new technology on soft error rates," in Proc. SELSE, 2011, pp. 486-492.
25. M. Gschwind, P. Hofstee, B. Flachs, M. Hopkins, Y. Watanabe, and T. Yamazaki, A Novel SIMD Architecture for the Cell Heterogeneous Chip-Multiprocessor, 2005. [Online]. Available: http://www. hotchips.org/ archives/hc17/2-Mon/HC17.S1/HC17.S1T1.pdf
26. AMD, The AMD Opteron Processor for High-End Embedded Designs, 2008. [Online]. Avilable: http://www.amd.com/es/Documents/42350B-Opteron-PB.pdf
27. IBM, Bladecenter H Chassis. [Online]. Available: http://www-03.ibm. com/systems/bladecenter/hardware/chassis/bladeh
28. Virtex-II Platform FPGAs : Complete Data Sheet (DS031). [Online]. Available: http://www.xilinx.com
29. H. Quinn, P. Graham, M. Wirthlin, B. Pratt, K. Morgan, M. Caffrey, and J. Krone, "A test methodology for determining space readiness of Xilinx SRAM-based FPGA devices and designs," IEEE Trans. Instrum. Meas., vol. 58, no. 10, pp. 3380-3395, Oct. 2009.
30. M. Kistler, J. Gunnels, D. Brokenshire, and B. Benton, "Programming the Linpack benchmark for Roadrunner," IBM J. Res. Develop., vol. 53, no. 5, pp. 736-746, Sep. 2009.
31. A. Petitet, R. C. Whaley, J. Dongarra, and A. Cleary, HPL-A Portable Implementation of the High-Performance Linpack Benchmark for Distributed-Memory Computers. [Online]. Available: http://netlib.org/benchmark/hpl
32. A. DuBois, C. Conner, S. Michalak, G. Taylor, and D. DuBois, "Application of the IBM cell processor to real-time cross-correlation of a large antenna array radio telescope," Los Alamos Nat. Lab., Los Alamos, NM, Tech. Rep. LA-UR-09-03483, 2009.
33. K. J. Bowers, B. J. Albright, L. Yin, W. Daughton, V. Roytershteyn, B. Bergen, and T. J. T. Kwan, "Advances in petascale kinetic plasma simulation with VPIC and Roadrunner," J. Phys., Conf. Ser., vol. 180, no. 1, p. 012-055, 2009.
34. A. Hands, P. Morris, K. Ryden, C. Dyer, P. Truscott, A. Chugg, and S. Parker, "Single event effects in power MOSFETS due to atmospheric and thermal neutrons," IEEE Trans. Nucl. Sci., vol. 58, no. 6, pp. 2687-2694, Dec. 2011.
35. A. Gelman, J. Carlin, H. Stern, and D. Rubin, Bayesian Data Analysis, 2nd ed. London, U.K.: Chapman & Hall, 2004.
36. Flux Calculation, 2008. [Online]. Available: http://seutest.com/cgi-bin/ FluxCalculator.cgi
37. S. Mukherjee, C. Weaver, J. Emer, S. Reinhardt, and T. Austin, "A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor," in Proc. 36th Annu. Int. Symp. MICRO, 2003, pp. 29-40.
38. A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S. Mukherjee, and R. Rangan, "Computing architectural vulnerability factors for addressbased structures," in Proc. 32nd ISCA, 2005, pp. 532-543.
39. F. Irom, "Guideline for ground radiation testing of microprocessors in the space radiation environment," Jet Propulsion Lab., Los Angeles, CA, JPL Pub. 08-13, 2008.