Driving source-line cell architecture for sub-1-V high-speed low-power applications

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 552-557

  Mizuno, Hiroyuki ^a,b,c   Nagano, Takahiro ^a,b,d,e  

^a IEEE

^b HITACHI LTD   (Japan)

^c OSAKA UNIVERSITY   (Japan)

^d KYOTO INSTITUTE OF TECHNOLOGY   (Japan)

^e KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC CIRCUITS; LSI CIRCUITS; MOSFET DEVICES;

DISTRIBUTED CACHE MEMORY SYSTEMS; DRIVING SOURCE LINE; STATIC NOISE MARGIN;

RANDOM ACCESS STORAGE;

EID: 0030121481     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499732     Document Type: Article

References (11)

1. A. P. Chandrakasan, S. Sheng, R. W. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473-484, Apr. 1992.
2. J. B. Burr and J. Shott, "A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS," in 1994 ISSCC Dig. Tech. Papers, Feb. 1994, pp. 84-85.
3. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, "1V high-speed digital circuit technology with 0.5 μm multi-threshold CMOS," in Proc. Sixth Annual IEEE Int. ASIC Conf. and Exhibit, 1993, pp. 186-189.
4. T. Sakata, M. Horiguchi, and K. Itoh, "Subthreshold-current reduction circuits for multi-gigabit DRAM's," in 1993 Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 45-46.
5. M. Horiguchi, T. Sakata, and K. Itoh, "Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's," in 1993 Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 47-48.
6. D. B. Lidsky and J. M. Rabaey, "Low-power design of memory intensive functions," in 1994 IEEE Symp. Low Power Electronics, 1994, pp. 16-17.
7. H. Mizuno and T. Nagano, "Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications," in 1995 Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 25-26.
8. F. Assaderaghi, S. Parke, P. K. Ko, and C. Hu, "A novel silicon-on-insulator (SOI) MOSFET for ultra low voltage operation," in 1994 IEEE Symp. Low Power Electronics, Oct. 1994, pp. 58-59.
9. K. Ishibashi, K. Takasugi, T. Yamanaka, T. Hashimoto, and K. Sasaki, "A 1 V TFT-load SRAM using a two-step word-voltage method," in 1992 ISSCC Dig. Tech. Papers, Feb. 1992, pp. 206-207.
10. S. W. Sun and P. G. Y. Tsui, "Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation," in 1994 IEEE Custom Integrated Circuits Conf., 1994, pp. 267-270.
11. Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi, and M. Aoki, "Sub-1 V swing bus architecture for future low-power ULSI's," in 1992 Symp. on VLSI Circuits Dig. Tech. Papers, June 1992, pp. 82-83.