Enhanced total ionizing dose tolerance of bulk CMOS transistors fabricated for ultra-low power applications

IEEE Transactions on Nuclear Science

Volumn 46, Issue 6 PART 1, 1999, Pages 1697-1701

  Xapsos, M A ^a   Summers, O P ^a   Jackson, E M ^a  

^a NAVAL RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INVASIVE HARDENING METHODS; LOCAL OXIDATION OF SILICON; PREDOMINANT FAILURE MODE; ULTRA LOW POWER;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; IONIZING RADIATION; LEAKAGE CURRENTS; MICROELECTRONICS; OXIDATION; SEMICONDUCTING SILICON; THRESHOLD VOLTAGE; TRANSISTORS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033342041     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.819141     Document Type: Article

References (9)

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