Statistically aware SRAM memory array design

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 25-30

  Grossar, Evelyn ^a,b   Stucchi, Michele ^a   Maex, Karen ^a,b   Dehaene, Wim ^b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; DELAY CONSTRAINTS; DESIGN APPROACHES; PERFORMANCE PARAMETERS; STAND-BY LEAKAGE; STATISTICAL INFORMATION; TECHNOLOGY SCALING; TECHNOLOGY VARIATIONS;

OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

DESIGN;

EID: 84886738383     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.122     Document Type: Conference Paper

References (20)

1. B. Cheng et al., "The impact of Random Doping Effects on CMOS SRAM Cell", ESSCIRC '04, 21-23 Sept. 2004, pp. 219-222
2. S.Zhang et al., "A Probabilistic Framework to estimate Full-Chip Subthreshold Leakage Power Distribution ConsideringWithin-Die and Die-to-Die P-T-V Variations", Proc. ISPLED '04, Newport Beach, California USA, Aug '04
3. R.Rao et al., "Statistical Estimation of leakage current considering inter and intra-die process variations", Proc. ISPLED '03, pp.84-89
4. S.Mukhopadhyay et al., "Modeling and Estimation of Failure Probability due to Parameter Variations in Nanoscale SRAMs for Yield Enhancement", Dig. of tech. Sym. on VLSI Circuits, 2004
5. R.Rao et al.,"Parametric Yield Analysis and Constrained Based Supply Voltage Optimization", ISQED '05, 21-23 March 2005, pp. 284-290
6. E. Grossar, "A yield-aware modeling methodology for nano-scaled SRAM designs", Proc. ICICDT '05, p. 33-36
7. A.Srivastava et al., "Statistical Optimization of Leakage Power Considering Process Variations using Dual-Vth and Sizing", DAC '04, June 7-11, San Diego, California, USA
8. S.Mukhopadhyay et al., "Statistical Design and Optimization of SRAM Cell for Yield Enhancement", IEEE/ACM ICCAD '04, 7-11 Nov. 2004, pp. 10-13
9. K. Itoh, "Low-Voltage Embedded RAMs in the Nanometer Era", Proc. ICICDT '05, pp. 235-242
10. A.J.Bhavnagarwala et al., "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability", IEEE JSSC vol.36, no. 4, April 2001
11. K.Roy et al., "Leakage current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS circuits", Proc. of the IEEE vol. 91, no.2, February 2003
12. P. Geens, et al., "A small granular controlled leakage reductions system for SRAMs", Proc. of ICMTD '05, 2005
13. Wang H., et al., "Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules ", Proc. DATE '05, 2005
14. E. Seevinck et al., "Static-Noise Margin Analysis of MOS SRAM Cells", IEEE JSSC vol. sc-22, no. 5, October 1987
15. R. Heald et al., "Variability in Sub-100nm SRAM Designs", IEEE/ACM ICCAD '04,7-11 nov. 2004, pp.347-352
16. R.W.Mann et al., "Ultralow-power SRAM technology", IBM J. RES & DEV. vol. 47, no. 5/6, Sept/Nov 2003, pp. 553-566
17. S.Akiyama, et al., "Concordant Memory-Array Design: An Integrated Statistical Approach for High-quality Gigabit-DRAM Design", Proc. ICICT '05
18. A. Papoulis, "Probability, Random Variables and Stochastic Process", New York: McGraw-Hill 1991, ISBN 0070484775
19. C. Rose, et al., "Mathematical Statistics with Mathematica", New York: Springer-Verlag 2002, ISBN 0387952349
20. J. Purviance et al., "Statistical Performance Sensitivitya Valuable Measure for Manufacturing Oriented CAD", IEEE MTT-S Digest, 1992