Physical and electrical performance limits of high-speed SiGeC HBTs- Part I: Vertical scaling

IEEE Transactions on Electron Devices

Volumn 58, Issue 11, 2011, Pages 3687-3696

  Schröter, Michael ^a,b   Wedel, Gerald ^a   Heinemann, Bernd ^c   Jungemann, Christoph ^d   Krause, Julia ^a   Chevalier, Pascal ^e   Chantre, Alain ^e  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IHP   (Germany)

^d RWTH AACHEN UNIVERSITY   (Germany)

^e STMICROELECTRONICS   (France)

Author keywords

Device scaling; device simulation; high performance bipolar technology; physical limits; SiGeC heterojunction bipolar transistor (HBT)

Indexed keywords

ELECTRIC RESISTANCE; HETEROJUNCTIONS;

BIPOLAR TECHNOLOGY; DEVICE SIMULATIONS; DEVICE-SCALING; PHYSICAL LIMITS; SIGEC HETEROJUNCTION BIPOLAR TRANSISTORS;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 84932938920     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2163722     Document Type: Article

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