Physical and electrical performance limits of high-speed SiGeC HBTs - Part II: Lateral scaling

IEEE Transactions on Electron Devices

Volumn 58, Issue 11, 2011, Pages 3697-3706

  Schröter, Michael ^a,b   Krause, Julia ^a   Rinaldi, Niccol ^c   Wedel, Gerald ^a   Heinemann, Bernd ^d   Chevalier, Pascal ^e   Chantre, Alain ^e  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF NAPLES FEDERICO II   (Italy)

^d IHP   (Germany)

^e STMICROELECTRONICS   (France)

Author keywords

device simulation; high performance bipolar technology; physical limits; SiGeC heterojunction bipolar transistor (HBT) device scaling

Indexed keywords

BIPOLAR TECHNOLOGY; COMPACT MODEL; DEVICE DESIGN; DEVICE SIMULATIONS; ELECTRICAL PERFORMANCE; ELECTRO-THERMAL SIMULATION; FIGURES OF MERITS; HIGH FREQUENCY PERFORMANCE; HIGH-SPEED; HIGHLY INTEGRATED; MILLIMETER-WAVE APPLICATIONS; PARASITIC CAPACITANCE; PEAK VALUES; PERFORMANCE LIMITS; PHYSICAL EFFECTS; PHYSICAL LIMITS; SAFE OPERATING AREA; SCALED DEVICES; SIGEC HETEROJUNCTION BIPOLAR TRANSISTORS; TEMPERATURE INCREASE; TERAHERTZ GAP; VERTICAL PROFILE;

CIRCUIT SIMULATION; COMPUTER SIMULATION; ELECTROSTATIC DEVICES; EQUIPMENT; HETEROJUNCTIONS; SILICON ALLOYS; TERAHERTZ WAVES;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 80054940602     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2163637     Document Type: Article

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