Analysis of communication delay bounds for network on chips

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 7-12

  Qian, Yue ^a   Lu, Zhonghai ^b   Dou, Wenhua ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS TECHNIQUES; CLOSED-FORM FORMULAE; COMMUNICATION DELAYS; DELAY BOUNDS; IN NETWORKS; NETWORK CALCULUS THEORIES; NETWORK CONTENTIONS; NETWORK ON CHIPS; PACKET DELAYS; PACKET DELIVERIES; RESOURCE CONTENTIONS; THEORETICAL BOUNDS; TOPOLOGY INDEPENDENTS;

DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY;

COMPUTER AIDED DESIGN;

EID: 64549140251     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796433     Document Type: Conference Paper

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